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data sheet february 1997 att3000 series field-programmable gate arrays features n high performance: ?up to 270 mhz toggle rates ?4-input lut delays <2.7 ns n user-programmable gate arrays ?unlimited reprogrammability ?easy design iteration through in-system logic changes n flexible array architecture: ?compatible arrays ranging from 1500 to 6000 gate logic complexity ?extensive register, combinatorial, and i/o capabilities ?low-skew clock nets ?high fan-out signal distribution ?internal 3-state bus capabilities ?ttl or cmos input thresholds ?on-chip oscillator ampli?r n standard product availability: ?low-power 0.55 ? cmos, static memory technology ?pin-for-pin compatible with xilinx* xc3000* and xc3100* families ?cost-effective for volume production ?100% factory pretested ?selectable con?uration modes n orca foundry for att3000 development system support n all fpgas processed on a qml-certi?d line n extensive packaging options description the cmos att3000 series field-programmable gate array (fpga) family provides a group of high- density, digital integrated circuits. their regular, extendable, ?xible, user-programmable array architecture is composed of a con?uration program store plus three types of con?urable elements: a perimeter of i/o blocks, a core array of logic blocks, and resources for interconnection. the general struc- ture of an fpga is shown in figure 1. the orca foundry for att3000 development sys- tem provides automatic place and route of netlists. logic and timing simulation are available as design veri?ation alternatives. the design editor is used for interactive design optimization and to compile the data pattern that represents the con?uration pro- gram. the fpga? user-logic functions and interconnec- tions are determined by the con?uration program data stored in internal static memory cells. the pro- gram can be loaded in any of several modes to accommodate various system requirements. the program data resides externally in an eeprom, eprom, or rom on the application circuit board, or on a ?ppy disk or hard disk. on-chip initialization logic provides for optional automatic loading of pro- gram data at powerup. a serial con?uration prom can provide a very simple serial con?uration pro- gram storage. * xilinx , xc3000, and xc3100 are registered trademarks of xilinx, inc. table 1. att3000 series fpgas fpga max logic gates typical gate range con?urable logic blocks array user i/os max flip- flops horizontal long lines con?uration data bits att3020 1,500 1,000?,500 64 8 x 8 64 256 16 14,779 att3030 2,000 1,500?,000 100 10 x 10 80 360 20 22,176 att3042 3,000 2,000?,000 144 12 x 12 96 480 24 30,784 att3064 4,500 3,500?,500 224 16 x 14 120 688 32 46,064 att3090 6,000 5,000?,000 320 20 x 16 144 928 40 64,160
data sheet att3000 series field-programmable gate arrays february 1997 2 lucent technologies inc. contents page performance .............................................................29 device performance .............................................29 logic block performance ......................................30 interconnect performance .....................................30 power ........................................................................32 power distribution .................................................32 power dissipation .................................................33 pin information .........................................................34 pin assignments .......................................................39 package thermal characteristics .............................50 package coplanarity .................................................51 package parasitics ...................................................51 absolute maximum ratings ......................................53 electrical characteristics ..........................................54 outline diagrams ......................................................68 terms and de?itions ...........................................68 44-pin plcc .........................................................68 68-pin plcc .........................................................69 84-pin plcc .........................................................70 100-pin qfp .........................................................71 100-pin tqfp .......................................................72 132-pin ppga ......................................................73 144-pin tqfp .......................................................74 160-pin qfp .........................................................75 175-pin ppga ......................................................76 208-pin sqfp .......................................................77 ordering information .................................................78 contents page features ..................................................................... 1 description ................................................................. 1 architecture ................................................................ 3 con?uration memory................................................ 4 i/o block ..................................................................... 5 summary of i/o options ......................................... 6 con?urable logic block ............................................ 7 programmable interconnect ....................................... 9 general-purpose interconnect ............................. 10 direct interconnect ............................................... 11 long lines ............................................................ 13 internal buses ...................................................... 14 crystal oscillator .................................................. 16 con?uration ............................................................ 17 initialization phase ............................................... 17 con?uration data ............................................... 19 con?uration modes ................................................ 22 master mode ........................................................ 22 peripheral mode ................................................... 24 slave mode .......................................................... 25 daisy chain .......................................................... 26 special con?uration functions .............................. 27 input thresholds ................................................... 27 readback ............................................................. 27 reprogram ........................................................... 28 done pull-up ...................................................... 28 done timing ....................................................... 28 reset timing ...................................................... 28 crystal oscillator division .................................... 28 table of contents
data sheet february 1997 att3000 series field-programmable gate arrays lucent technologies inc. 3 architecture the perimeter of con?urable i/o blocks (iobs) pro- vides a programmable interface between the internal logic array and the device package pins. the array of con?urable logic blocks (clbs) performs user- speci?d logic functions. the interconnect resources are programmed to form networks, carrying logic signals among blocks, analogous to printed-circuit board traces connecting msi/ssi packages. the blocks?logic functions are implemented by programmed look-up tables. functional options are implemented by program-controlled multiplexers. interconnecting networks between blocks are implemented with metal segments joined by program- controlled pass transistors. these functions of the fpga are established by a con?uration program which is loaded into an internal, distributed array of con?uration memory cells. the con?uration program is loaded into the fpga at powerup and may be reloaded on command. the fpga includes logic and control signals to implement automatic or passive con?uration. program data may be either bit serial or byte parallel. the orca foundry for att3000 devel- opment system generates the con?uration program bit stream used to con?ure the fpga. the memory loading process is independent of the user logic func- tions. figure 1. field-programmable gate array structure
data sheet att3000 series field-programmable gate arrays february 1997 4 lucent technologies inc. con?uration memory the static memory cell used for the con?uration mem- ory in the fpga has been designed speci?ally for high reliability and noise immunity. integrity of the fpga con?uration memory based on this design is ensured even under various adverse conditions. com- pared with other programming alternatives, static mem- ory is believed to provide the best combination of high density, high performance, high reliability, and compre- hensive testability. as shown in figure 2, the basic memory cell consists of two cmos inverters plus a pass transistor used for writing and reading cell data. the cell is only written to during con?uration and only read from during read- back. during normal operation, the cell provides contin- uous control and the pass transistor is off and does not affect cell stability. this is quite different from the opera- tion of conventional memory devices, in which the cells are frequently read and rewritten. the memory cell outputs q and q use full ground and v cc levels and provide continuous, direct control. the additional capacitive load and the absence of address decoding and sense ampli?rs provide high stability to the cell. due to their structure, the con?uration mem- ory cells are not affected by extreme power supply excursions or very high levels of alpha particle radia- tion. soft errors have not been observed in reliability testing. two methods of loading con?uration data use serial data, while three use byte-wide data. the internal con- ?uration logic utilizes framing information, embedded in the program data by the orca foundry develop- ment system, to direct memory cell loading. the serial data framing and length count preamble provide pro- gramming compatibility for mixes of various lucent pro- grammable gate arrays in a synchronous, serial, daisy- chain fashion. figure 2. static con?uration memory cell read or write data q q configuration control 5-3101(f)
data sheet february 1997 att3000 series field-programmable gate arrays lucent technologies inc. 5 i/o block each user-con?urable i/o block (iob), shown in figure 3, provides an interface between the external package pin of the device and the internal user logic. each iob includes both registered and direct input paths and a programmable 3-state output buffer which may be driven by a registered or direct output signal. con?uration options allow each iob an inversion, a controlled slew rate, and a high-impedance pull-up. each input circuit also provides input clamping diodes to provide electrostatic protection and circuits to inhibit latch-up produced by input currents. the input buffer portion of each iob provides threshold detection to translate external signals applied to the package pin to internal logic levels. the global input- buffer threshold of the iob can be programmed to be compatible with either ttl or cmos levels. the buff- ered input signal drives the data input of a storage element which may be con?ured as a positive-edge triggered d ?p-?p or a low-level transparent latch. the sense of the clock can be inverted (negative edge/high transparent) as long as all iobs on the same clock net use the same clock sense. clock/load signals (iob pins .ik and .ok) can be selected from either of two die edge metal lines. i/o storage elements are reset during con- ?uration or by the active-low chip reset input. both direct input (from iob pin .i) and registered input (from iob pin .q) signals are available for interconnect. figure 3. input/output block 5-3102(f) out invert 3-state invert output select slew rate passive pull up program-controlled memory cells v cc output buffer flip- flop d q r ttl or cmos input threshold flip- flop q d r or latch .lk .t = programmable interconnection point or pip ck2 (global reset) i/o pad .o .i .q 3-state out direct in registered in ck1 program- controlled multiplexer output enable .ok
data sheet att3000 series field-programmable gate arrays february 1997 6 lucent technologies inc. i/o block (continued) for reliable operation, inputs should have transition times of less than 100 ns and should not be left ?at- ing. floating cmos input-pin circuits might be at threshold and produce oscillations. this can produce additional power dissipation and system noise. a typical hysteresis of about 300 mv reduces sensitivity to input noise. each user iob includes a programmable high-impedance pull-up resistor which is selected by the program to provide a constant high for otherwise undriven package pins. normal cmos handling precautions should be observed. flip-?p loop delays for the iob and logic block ?p- ?ps are approximately 3 ns. this short delay provides good performance under asynchronous clock and data conditions. short loop delays minimize the probability of a metastable condition which can result from asser- tion of the clock during data transitions. because of the short loop delay characteristic in the fpga, the iob ?p-?ps can be used to synchronize external signals applied to the device. when synchronized in the iob, the signals can be used internally without further con- sideration of their clock relative timing, except as it applies to the internal logic and routing path delays. output buffers of the iobs provide cmos-compatible 4 ma source-or-sink drive for high fan-out cmos or ttl compatible signal levels. the network driving iob pin .o becomes the registered or direct data source for the output buffer. the 3-state control signal (iob pin .t) can control output activity. an open-drain type output may be obtained by using the same signal for driving the output and 3-state signal nets so that the buffer out- put is enabled only for a low. con?uration program bits for each iob control features such as optional output register, logical signal inversion, and 3-state and slew rate control of the out- put. the program-controlled memory cells in figure 3 control the following options: n logical inversion of the output is controlled by one con?uration program bit per iob. n logical 3-state control of each iob output buffer is determined by the states of con?uration program bits which turn the buffer on or off or select the output buffer 3-state control interconnection (iob pin .t). when this iob output control signal is high, a logic 1, the buffer is disabled and the package pin is high impedance. when this iob output control signal is low, a logic 0, the buffer is enabled and the package pin is active. inversion of the buffer 3-state control logic sense (output enable) is controlled by an addi- tional con?uration program bit. n direct or registered output is selectable for each iob. the register uses a positive-edge, clocked ?p-?p. the clock source may be supplied (iob pin .ok) by either of two metal lines available along each die edge. each of these lines is driven by an invertible buffer. n increased output transition speed can be selected to improve critical timing. slower transitions reduce capacitive load peak currents of noncritical outputs and minimize system noise. n a high-impedance pull-up resistor may be used to prevent unused inputs from ?ating. summary of i/o options n inputs ?irect ?lip-?p/latch ?mos/ttl threshold (chip inputs) ?ull-up resistor/open circuit n outputs ?irect/registered ?nverted/not ?-state/on/off ?ull speed/slew limited ?-state/output enable (inverse)
data sheet february 1997 att3000 series field-programmable gate arrays lucent technologies inc. 7 con?urable logic block the array of con?urable logic blocks (clbs) provides the functional elements from which the user? logic is constructed. the logic blocks are arranged in a matrix within the perimeter of iobs. the att3020 has 64 such blocks arranged in eight rows and eight columns. the orca foundry development system is used to com- pile the con?uration data for loading into the internal con?uration memory to de?e the operation and inter- connection of each block. user de?ition of clbs and their interconnecting networks may be done by auto- matic translation from a schematic capture logic dia- gram or optionally by installing library or user macros. each clb has a combinatorial logic section, two ?p- ?ps, and an internal control section; see figure 4 below. there are ?e logic inputs (.a, .b, .c, .d, and .e); a common clock input (.k); an asynchronous direct reset input (.rd); and an enable clock (.ec). all may be driven from the interconnect resources adjacent to the blocks. each clb also has two outputs (.x and .y) which may drive interconnect networks. data input for either ?p-?p within a clb is supplied from the function f or g outputs of the combinatorial logic, or the block input, data-in (.di). both ?p-?ps in each clb share the asynchronous reset (.rd) which, when enabled and high, is dominant over clocked inputs. all ?p-?ps are reset by the active-low chip input, reset , or during the con?uration process. the ?p-?ps share the enable clock (.ec) which, when low, recirculates the ?p-?ps?present states and inhib- its response to the data-in or combinatorial function inputs on a clb. the user may enable these control inputs and select their sources. the user may also select the clock net input (.k), as well as its active sense within each logic block. this programmable inversion eliminates the need to route both phases of a clock signal throughout the device. flexible routing allows use of common or individual clb clocking. the combinatorial logic portion of the logic block uses a 32 x 1 look-up table to implement boolean functions. variables selected from the ?e logic inputs and the two internal block ?p-?ps are used as table address inputs. the combinatorial propagation delay through the network is independent of the logic function gener- ated and is spike-free for single-input variable changes. this technique can generate two independent logic functions of up to four variables each as shown in fig- ure 5a, or a single function of ?e variables as shown in figure 5b, or some functions of seven variables as shown in figure 5c. figure 4. con?urable logic block 0 1 mux 0 1 mux d q rd d q rd ??(enable) data in logic variables .a .b .c .e .d enable clock qx combinatorial function qx f g .x .y ??(inhibit) (global reset) .ec .k .rd .di f din g clb outputs qx f f din g g qy clock 5-3103(f) direct reset
data sheet att3000 series field-programmable gate arrays february 1997 8 lucent technologies inc. con?urable logic block (continued) 5a. combinatorial logic option 1 generates two functions of four variables each. one variable, a, must be common to both func- tions. the second and third variables can be any choice among b, c, qx, and qy. the fourth variable can be either d or e. 5b. combinatorial logic option 2 generates any function of ?e variables: a, d, e, and two choices among b, c, qx, qy. 5c. combinatorial logic option 3 allows variable e to select between two functions of four variables: both have common inputs, a and d, and any choice among b, c, qx, and qy for the remaining two variables. option 3 can then implement some functions of six or seven variables. figure 5. combinatorial logic diagram figure 6 shows a modulo 8 binary counter with parallel enable. it uses one clb of each type. the partial func- tions of six or seven variables are implemented by using the input variable (.e) to dynamically select between two functions of four different variables. for the two functions of four variables each, the indepen- dent results (f and g) may be used as data inputs to either ?p-?p or logic block output. for the single func- tion of ?e variables and merged functions of six or seven variables, the f and g outputs are identical. symmetry of the f and g functions and the ?p-?ps allows the interchange of clb outputs to optimize routing ef?iencies of the networks interconnecting the logic and iobs. figure 6. c8bcp macro a b c d e qx qy any function of up to 4 variables f any function of up to 4 variables g qy qx a b c d e any function of 5 variables a b c d e qx qy f g a b c d qx qy a b c d e qx qy f g any function of up to 4 variables any function of up to 4 variables m u x 5a 5b 5c 5-3104(f) clock parallel clock terminal count d0 q0 d q q1 d1 d2 q2 d q function of 6 variables d q function of 5 variables dual function of enable enable 4 variables 5-3105(f)
lucent technologies inc. 9 data sheet february 1997 att3000 series field-programmable gate arrays programmable interconnect programmable interconnection resources in the fpga provide routing paths to connect inputs and outputs of the iobs and logic blocks into logical networks. inter- connections between blocks are composed from a two- layer grid of metal segments. specially designed pass transistors, each controlled by a con?uration bit, form programmable interconnect points (pips) and switching matrices used to implement the necessary connections between selected metal segments and block pins. figure 7 is an example of a routed net. the orca foundry development system provides automatic rout- ing of these interconnections. interactive routing is also available for design optimization. the inputs of the logic or iobs are multiplexers which can be programmed to select an input network from the adjacent interconnect segments. since the switch connections to block inputs are unidirectional (as are block outputs), they are usable only for block input connection and not routing. figure 8 illustrates routing access to logic block input variables, control inputs, and block outputs. three types of metal resources are provided to accom- modate various network interconnect requirements: n general-purpose interconnect n direct connection n long lines (multiplexed buses and wide-and gates) figure 7. example of routing resources figure 8. clb input and output routing
data sheet att3000 series field-programmable gate arrays february 1997 10 lucent technologies inc. programmable interconnect (continued) general-purpose interconnect general-purpose interconnect, as shown in figure 9, consists of a grid of ?e horizontal and ?e vertical metal segments located between the rows and col- umns of logic and iobs. each segment is the height or width of a logic block. switching matrices join the ends of these segments and allow programmed interconnec- tions between the metal grid segments of adjoining rows and columns. the switches of an unprogrammed device are all nonconducting. the connections through the switch matrix may be established by automatic or interactive routing by selecting the desired pairs of matrix pins to be connected or disconnected. the legitimate switching matrix combinations for each pin are indicated in figure 10. special buffers within the general interconnect areas provide periodic signal isolation and restoration for improved performance of lengthy nets. the intercon- nect buffers are available to propagate signals in either direction on a given general interconnect segment. these bidirectional (bidi) buffers are found adjacent to the switching matrices, above and to the right. the other pips adjacent to the matrices are accessed to or from long lines. the development system automatically de?es the buffer direction based on the location of the interconnection network source. the delay calculator in the orca foundry development system automatically calculates and displays the block, interconnect, and buffer delays for any paths selected. generation of the simulation netlist with a worst-case delay model is also provided by the development system. some of the interconnect pips are directional, as indicated below: n nd is a nondirectional interconnection. n d:h->v is a pip which drives from a horizontal to a vertical line. n d:v->h is a pip which drives from a vertical to a horizontal line. n d:c->t is a t-pip which drives from a cross of a t to the tail. n d:cw is a corner pip which drives in the clockwise direction. n p0 indicates the pip is nonconducting; p1 is on. figure 9. fpga general-purpose interconnect figure 10. switch matrix interconnection options 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
lucent technologies inc. 11 data sheet february 1997 att3000 series field-programmable gate arrays programmable interconnect (continued) direct interconnect direct interconnect (shown in figure 11) provides the most ef?ient implementation of networks between adjacent logic or iobs. signals routed from block to block using the direct interconnect exhibit minimum interconnect propagation and use no general intercon- nect resources. for each clb, the .x output may be connected directly to the .b input of the clb immedi- ately to its right and to the .c input of the clb to its left. the .y output can use direct interconnect to drive the .d input of the block immediately above, and the .a input of the block below. direct interconnect should be used to maximize the speed of high-performance portions of logic. where logic blocks are adjacent to iobs, direct connect is provided alternately to the iob inputs (.i) and outputs (.o) on all four edges of the die. the right edge provides additional direct connects from clb out- puts to adjacent iobs. direct interconnections of iobs with clbs are shown in figure 12. figure 11. direct interconnect
data sheet att3000 series field-programmable gate arrays february 1997 12 lucent technologies inc. programmable interconnect (continued) figure 12. att3020 die edge i/o blocks with direct access to adjacent clb
data sheet february 1997 att3000 series field-programmable gate arrays lucent technologies inc. 13 programmable interconnect (continued) long lines the long lines bypass the switch matrices and are intended primarily for signals which must travel a long distance, or must have minimum skew among multiple destinations. long lines, shown in figure 13, run vertically and horizontally the height or width of the interconnect area. each interconnection column has three vertical long lines, and each interconnection row has two horizontal long lines. additionally, two long lines are located adjacent to the outer sets of switching matrices. two vertical long lines in each column are connectable half-length lines, except on the att3020, where only the outer long lines serve that function. long lines can be driven by a logic block or iob output on a column-by-column basis. this capability provides a common low-skew control or clock line within each column of logic blocks. interconnections of these long lines are shown in figure 14. isolation buffers are pro- vided at each input to a long line and are enabled auto- matically by the development system when a connection is made. figure 13. horizontal and vertical long lines in the fpga 3- -
data sheet att3000 series field-programmable gate arrays february 1997 14 lucent technologies inc. programmable interconnect (continued) a buffer in the upper left corner of the fpga chip drives a global net which is available to all .k inputs of logic blocks. using the global buffer for a clock signal pro- vides a skew-free, high fan-out, synchronized clock for use at any or all of the i/o and logic blocks. con?ura- tion bits for the .k input to each logic block can select this global line, or another routing resource, as the clock source for its ?p-?ps. this net may also be pro- grammed to drive the die edge clock lines for iob use. an enhanced speed, cmos threshold, offers direct access to this buffer and is available at the second pad from the top of the left die edge. a buffer in the lower right corner of the array drives a horizontal long line that can drive programmed connec- tions to a vertical long line in each interconnection column. this alternate buffer also has low skew and high fan-out. the network formed by this alternate buf- fer? long lines can be selected to drive the .k inputs of the logic blocks. cmos threshold, high-speed access to this buffer is available from the third pad from the bottom of the right die edge. internal buses a pair of 3-state buffers is located adjacent to each clb. these buffers allow logic to drive the horizontal long lines. logical operation of the 3-state buffer controls allows them to implement wide multiplexing functions. any 3-state buffer input can be selected as drive for the horizontal long line bus by applying a low logic level on its 3-state control line (see figure 15a). the user is required to avoid contention that can result from multiple drivers with opposing logic levels. control of the 3-state input by the same signal that drives the buffer input creates an open-drain wired-and function. a logical high on both buffer inputs creates a high impedance which represents no contention. a logical low enables the buffer to drive the long line low (see figure 15b). pull-up resistors are available at each end of the long line to provide a high output when all con- nected buffers are nonconducting. this forms fast, wide gating functions. when data drives the inputs and sep- arate signals drive the 3-state control lines, these buff- ers form multiplexers (3-state buses). in this case, care must be used to prevent contention through multiple active buffers of con?cting levels on a common line. figure 16 shows 3-state buffers, long lines, and pull-up resistors. figure 14. programmable interconnection of long lines 3-state
data sheet february 1997 att3000 series field-programmable gate arrays lucent technologies inc. 15 programmable interconnect (continued) figure 15a. 3-state buffers implement a wired-and function figure 15b. 3-state buffers implement a multiplexer figure 16. lower-right corner of att3020 5-3106(f) z = d a d b d c ?... ?d n (low) d n d c d b d a v cc v cc 5-3107(f) z = d a ?a + d b ?b + d c ?c + ... + d n ?n d n d c d b d a a b c n weak keeper circuit p47 p48 bcl kin hg hh rst o p46 p43 p42 p41 p40 p g m .l .lk .q.ok .o gg gh horizontal long line pull-up resistor horizontal long line oscillator amplifier output direct input of p47 to auxiliary buffer crystal oscillator buffer 3-state input 3-state control 3-state buffer alternate buffer oscillator amplifier input 3 vertical long lines per column global net bidirectional interconnect buffers o s c 5-3108(f)
data sheet att3000 series field-programmable gate arrays february 1997 16 lucent technologies inc. programmable interconnect (continued) crystal oscillator figure 16 shows the location of an internal high-speed inverting ampli?r which may be used to implement an on-chip crystal oscillator. it is associated with the auxil- iary buffer in the lower right corner of the die. when the oscillator is con?ured and connected as a signal source, two special user iobs are also con?ured to connect the oscillator ampli?r with external crystal oscillator components as shown in figure 17. a divide- by-two option is available to ensure symmetry. the oscillator circuit becomes active before con?uration is complete in order to allow the oscillator to stabilize. actual internal connection is delayed until completion of con?uration. in figure 17, the feedback resistor, r1, between output and input biases the ampli?r at threshold. the value should be as large as is practical to minimize loading of the crystal. the inversion of the ampli?r, together with the r-c networks and an at cut series resonant crystal, produces the 360?phase shift of the pierce oscillator. a series resistor, r2, may be included to add to the ampli?r output impedance when needed for phase shift control or crystal resistance matching, or to limit the ampli?r input swing to control clipping at large amplitudes. excess feedback voltage may be corrected by the ratio of c2/c1. the ampli?r is designed to be used from 1 mhz to one-half the speci- ?d clb toggle frequency. use at frequencies below 1 mhz may require individual characterization with respect to a series resistance. crystal oscillators above 20 mhz generally require a crystal which operates in a third overtone mode, where the fundamental frequency must be suppressed by an inductor across c2. when the oscillator inverter is not used, these iobs and their package pins are available for general user i/o. suggested component values: r1?.5 m w to 1 m w r2? k w to 1 k w (may be required for low frequency, phase shift, and/or compensation level for crystal q) c1, c2?0 pf to 40 pf y1? mhz to 20 mhz at cut series resonant figure 17. crystal oscillator inverter pin 44-pin plcc 68-pin plcc 84-pin plcc 100-pin 132-pin ppga 144-pin tqfp 160-pin qfp 175-pin ppga 208-pin sqfp qfp tqfp xtal1 (out) 30 47 57 82 79 p13 75 82 t14 110 xtal2 (in) 26 43 53 76 73 m13 69 76 p15 100 r1 r2 c2 c1 xtal1 (out) xtal2 (in) alternate clock buffer internal external d q y1 l third overtone only 5-3109(f)
lucent technologies inc. 17 data sheet february 1997 att3000 series field-programmable gate arrays con?uration initialization phase an internal power-on-reset circuit is triggered when power is applied. when v cc reaches the voltage where portions of the fpga begin to operate (2.5 v to 3 v), the programmable i/o output buffers are disabled and a high-impedance pull-up resistor is provided for the user i/o pins. a time-out delay is initiated to allow the power supply voltage to stabilize. during this time, the power- down mode is inhibited. the initialization state time-out (about 11 ms to 33 ms) is determined by a 14-bit counter driven by a self-generated, internal timer. this nominal 1 mhz timer is subject to variations with pro- cess, temperature, and power supply over the range of 0.5 mhz to 1.5 mhz. as shown in table 2, ?e con?u- ration mode choices are available, as determined by the input levels of three mode pins: m0, m1, and m2. in master con?uration mode, the fpga becomes the source of con?uration clock (cclk). beginning con- ?uration of devices using peripheral or slave modes must be delayed long enough for their initialization to be completed. an fpga with mode lines selecting a master con?uration mode extends its initialization state using four times the delay (43 ms to 130 ms) to ensure that all daisy-chained slave devices it may be driving will be ready, even if the master is very fast and the slave(s), very slow (see figure 18). at the end of initialization, the fpga enters the clear state where it clears con?uration memory. the active-low, open- drain initialization signal init indicates when the initial- ization and clear states are complete. the fpga tests for the absence of an external active-low reset before it makes a ?al sample of the mode lines and enters the con?uration state. an external wired-and of one or more init pins can be used to control con?uration by the assertion of the active-low reset of a master mode device or to signal a processor that the fpgas are not yet initialized. if a con?uration has begun, a reassertion of reset for a minimum of three internal timer cycles will be recog- nized and the fpga will initiate an abort, returning to the clear state to clear the partially loaded con?ura- tion memory words. the fpga will then resample reset and the mode lines before reentering the con- ?uration state. a reprogram is initiated when a con?ured fpga senses a high-to-low transition on the done/ pr og package pin. the fpga returns to the clear state where con?uration memory is cleared and mode lines resampled, as for an aborted con?uration. the com- plete con?uration program is cleared and loaded dur- ing each con?uration program cycle. table 2. con?uration modes m0 m1 m2 clock mode data 0 0 0 active master bit serial 0 0 1 active master byte wide (address = 0000 up) 0 1 0 reserved 0 1 1 active master byte wide (address = ffff down) 1 0 0 reserved 1 0 1 active peripheral byte wide 1 1 0 reserved 1 1 1 passive slave bit serial
data sheet att3000 series field-programmable gate arrays february 1997 18 lucent technologies inc. con?uration (continued) figure 18. state diagram of con?uration process for powerup and reprogram 5-3110(f) initialization power-on time delay clear configuration memory yes reset active no test mode pins configuration program mode operational mode start-up init = low user i/o pins with high-impedance pull-up hdc = high ldc = low active reset powerdown no hdc, ldc or pull-up inactive pwrd wn active reset operates on user logic low on done/pr og and reset active pwrd wn length count control allows a system of multiple fpgas in assorted sizes to begin operation in a syn- chronized fashion. the con?uration program gener- ated by the orca foundry development system begins with a preamble of 111111110010 (binary), fol- lowed by a 24-bit length count representing the total number of con?uration clocks needed to complete loading of the con?uration program(s). the data fram- ing is shown in figure 19. all fpgas connected in series read and shift preamble and length count in (on positive) and out (on negative) cclk edges. an fpga which has received the preamble and length count then presents a high data out until it has intercepted the appropriate number of data frames. when the con?u- ration program memory of an fpga is full and the length count does not compare, the fpga shifts any additional data through, as it did for preamble and length count. when the fpga con?uration memory is full and the length count compares, the fpga will execute a syn- chronous start-up sequence and become operational (see figure 20 on page 20). two cclk cycles after the completion of loading con?uration data, the user i/o pins are enabled as con?ured. as selected in orca foundry, the internal user-logic reset is released either one clock cycle before or after the i/o pins become active. a similar timing selection is program- mable for the done/ pr og output signal. done/ pr og may also be programmed to be an open drain or include a pull-up resistor to accommodate wired- anding. the high during con?uration (hdc) and low during con?uration ( ldc ) are two user i/o pins which are driven active when an fpga is in initialization, clear, or con?ure states. these signals and done/ pr og provide for control of external logic signals such as reset, bus enable, or prom enable during con?uration. for parallel master con?uration modes, these signals provide prom enable control and allow the data pins to be shared with user logic signals. user i/o inputs can be programmed to be either ttl or cmos compatible thresholds. at powerup, all inputs have ttl thresholds and can change to cmos thresh- olds at the completion of con?uration, if the user has selected cmos thresholds. the threshold of pwrd wn and the direct clock inputs are ?ed at a cmos level. if the crystal oscillator is used, it will begin operation before con?uration is complete to allow time for stabilization before it is connected to the internal circuitry.
data sheet february 1997 att3000 series field-programmable gate arrays lucent technologies inc. 19 con?uration (continued) con?uration data con?uration data to de?e the function and interconnection within an fpga are loaded from an external storage at powerup and on a reprogram signal. several methods of automatic and controlled loading of the required data are available. logic levels applied to mode selection pins at the start of con?uration time determine the method to be used (see table 2). the data may be either bit-serial or byte-parallel, depending on the con?uration mode. various lucent programmable gate arrays have different sizes and numbers of data frames. for the att3020, con- ?uration requires 14779 bits for each device, arranged in 197 data frames. an additional 40 bits are used in the header (see figure 20). * the fpga devices require four dummy bits minimum. figure 19. internal con?uration data structure 11111111 0010 < 24-bit length count > 1111 0 < data frame # 001 > 111 0 < data frame # 002 > 111 0 < data frame # 003 > 111 . . . . . . . . . . . . ?dummy bits* ?preamble code ?configuration program length ?dummy bits (4 bits minimum) 197 configuration data frames (each frame consists of: a start bit (0) a 71-bit data field three stop bits postamble code (4 bits minimum) repeated for each logic cell array in a daisy chain 0 < data frame # 196 > 111 0 < data frame # 197 > 111 1111 for att3020 header program data )
data sheet att3000 series field-programmable gate arrays february 1997 20 lucent technologies inc. con?uration (continued) note: the length count produced by the bit stream generation program = [(40-bit preamble + sum of program data + 1 per daisy-chain device) rounded up to a multiple of 8] ?(2 k 4), where k is a function of done and reset timing selected. an additional 8 is added if the roundup increment is less than k. k additional clocks are needed to complete start-up after length count is reached. * the con?uration data consists of a composite 40-bit preamble/length count, followed by one or more concatenated fpga programs, separated by 4-bit postambles. an additional ?al postamble bit is added for each slave device, and the result rounded up to byte boundary. the length count is two less than the number of resulting bits. timing of the assertion of done and termination of the internal reset may each be programmed to occur one cycle before or after the i/o outputs become active. figure 20. fpga con?uration and start-up table 3. att3000 device con?uration data device att3020 att3030 att3042 att3064 att3090 gates 1500 2000 3000 4500 6000 clbs (row x column) 64 (8 x 8) 100 (10 x 10) 144 (12 x 12) 224 (16 x 14) 320 (20 x 16) iobs 64 80 96 120 144 flip-?ps 256 360 480 688 928 bits-per-frame (with 1 start/3 stop) 75 92 108 140 172 frames 197 241 285 329 373 program data = bits * frames + 4 (excludes header) 14779 22176 30784 46064 64160 prom size (bits) = program data + 40-bit headers 14819 22216 30824 46104 64200 preamble length count 12 24 75 stop data frame start start 4 3 last frame 4 postamble 3 stop length count* weak pull-up prog internal reset i/o active done dout lead device high 1/2 clock cycle delay from data input data 3 5-3111(f)
lucent technologies inc. 21 data sheet february 1997 att3000 series field-programmable gate arrays con?uration (continued) the speci? data format for each device is produced by the bit stream generation program, and one or more of these ?es can then be combined and appended to a length count preamble and be transformed into a prom format ?e by the prom generation program of the orca foundry development system. the tie option of the bit stream generation program de?es output levels of unused blocks of a design and con- nects these to unused routing resources. this prevents indeterminate levels which might produce parasitic supply currents. this tie option can be omitted for quick breadboard iterations where a few additional ma of i cc are acceptable. the con?uration bit stream begins with high preamble bits, a 4-bit preamble code, and a 24-bit length count. when con?uration is initiated, a counter in the fpga is set to 0 and begins to count the total number of con- ?uration clock cycles applied to the device. as each con?uration data frame is supplied to the fpga, it is internally assembled into a data word. as each data word is completely assembled, it is loaded in parallel into one word of the internal con?uration memory array. the con?uration loading process is complete when the current length count equals the loaded length count and the required con?uration program data frames have been written. internal user ?p-?ps are held reset during con?uration. two user-programmable pins are de?ed in the uncon- ?ured fpga: high during con?uration (hdc) and low during con?uration ( ldc ), and done/ pr og may be used as external control signals during con?uration. in master mode con?urations, it is convenient to use ldc as an active-low eprom chip enable. after the last con?uration data bit is loaded and the length count compares, the user i/o pins become active. options in the bit stream generation program allow timing choices of one clock earlier or later for the timing of the end of the internal logic reset and the assertion of the done signal. the open-drain done/ pr og output can be and-tied with multiple fpgas and used as an active- high ready, an active-low prom enable, or a reset to other portions of the system. the state diagram of figure 18 illustrates the con?uration process.
data sheet att3000 series field-programmable gate arrays february 1997 22 lucent technologies inc. con?uration modes master mode in master mode, the fpga automatically loads con?u- ration data from an external memory device. there are three master modes which use the internal timing source to supply the con?uration clock (cclk) to time the incoming data. serial master mode uses serial con- ?uration data supplied to data-in (din) from a syn- chronous serial source such as the serial con?uration prom shown in figure 21. parallel master low and master high modes automatically use parallel data sup- plied to the d[7:0] pins in response to the 16-bit address generated by the fpga. figure 22 shows an example of the parallel master mode connections required. the fpga hex starting address is 0000 and increments for master low mode, and it is ffff and decrements for master high mode. these two modes provide address compatibility with microprocessors which begin execution from opposite ends of memory. for master high or low, data bytes are read in parallel by each read clock ( rclk ) and internally serialized by the con?uration clock. as each data byte is read, the least signi?ant bit of the next byte, d0, becomes the next bit in the internal serial con?uration word. one master mode fpga can be used to interface the con?uration program-store, and pass additional concatenated con?uration data to additional fpgas in a serial daisy-chain fashion. cclk is provided for the slaved devices, and their serialized data is supplied from dout to din, dout to din, etc. note: the serial con?uration prom supports automatic loading of con?uration programs up to 36/64/128 kbits. multiple devices can be cascaded to support additional fpgas. an early done inhibits the data output one cclk cycle before the fpga i/o becomes active. figure 21. master serial mode 5-3112(c) during configuration the 5 k w m2 pull-down resistor overcomes the internal pull-up, but it allows m2 to be user i/o. m0 m1 pwrdwn +5 v dout m2 hdc ldc other i/o pins att3000 series fpga general- purpose user i/o pins * * reset system reset d/p cclk din ce clk data oe/reset att1700a ceo (high resets the address pointer) cascaded att1700a memory optional identical slave fpgas configured the same ce clk data init oe/reset
data sheet february 1997 att3000 series field-programmable gate arrays lucent technologies inc. 23 con?uration modes (continued) figure 22. master parallel mode 5-3113(f) m0 m1 pwrdwn fpga +5 v hdc other rclk i/o pins * * data bus general- purpose user i/o pns 5 k w dout m2 init reset a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 8 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 eprom oe ce d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 (2k x 8 or larger) system user control of higher order from address bits can be used to select from alternative configurations cclk +5 v 5 k w ldc reset d/ p
data sheet att3000 series field-programmable gate arrays february 1997 24 lucent technologies inc. con?uration modes (continued) peripheral mode peripheral mode provides a simpli?d interface through which the device may be loaded byte-wide, as a processor peripheral. figure 23 shows the peripheral mode connections. processor write cycles are decoded from the com- mon assertion of the active-low write strobe ( ws ), and two active-low and one active-high chip selects ( cs0 , cs1 , cs2). if all of these signals are not available, the unused inputs should be driven to their respective active levels. the fpga will accept 1 byte of con?uration data on the d[7:0] inputs for each selected processor write cycle. each byte of data is loaded into a buffer register. the fpga generates a cclk from the internal timing generator and serializes the parallel input data for internal framing or for succeeding slaves on data out (dout). an output high on ready/ b usy pin indicates the completion of loading for each byte when the input register is ready for a new byte. as with master modes, peripheral mode may also be used as a lead device for a daisy-chain of slave devices. figure 23. peripheral mode reprogram +5 v address bus control signals address decode logic 8 general- purpose user i/o other i/o pins ldc hdc m2 dout cclk cs0 d[7:0] cs1 cs2 ws rdy/busy init d/p reset d[7:0] m0 m1 pwrdwn * * +5 v data bus 5 k w oc 5-3114(f)
data sheet february 1997 att3000 series field-programmable gate arrays lucent technologies inc. 25 con?uration modes (continued) slave mode slave mode provides a simple interface for loading the fpga con?uration as shown in figure 24. serial data is supplied in conjunction with a synchronizing input clock. most slave mode applications are in daisy-chain con?u- rations in which the data input is supplied by the previous fpga? data out, while the clock is supplied by a lead device in master or peripheral mode. data may also be supplied by a processor or other special circuits. figure 24. slave mode 5-3115(f) microcomputer i/o port strb other d3 d2 d5 d4 d6 d7 d1 +5 v reset d/p reset init * * general- purpose user i/o i/o pins d0 fpga ldc hdc dout m2 5 k w +5 v m0 m1 pwrdwn cclk din system reset
data sheet att3000 series field-programmable gate arrays february 1997 26 lucent technologies inc. con?uration modes (continued) daisy chain the orca foundry for att3000 development system is used to create a composite con?uration bit stream for selected fpgas including a preamble, a length count for the total bit stream, multiple concatenated data programs, a postamble, plus an additional ?l bit per device in the serial chain. after loading and passing on the preamble and length count to a possible daisy chain, a lead device will load its con?uration data frames while providing a high dout to possible down- stream devices as shown in figure 25. loading contin- ues while the lead device has received its con?uration program and the current length count has not reached the full value. additional data is passed through the lead device and appears on the data out (dout) pin in serial form. the lead device also generates the cclk to synchronize the serial output data and data in of downstream fpgas. data is read in on din of slave devices by the positive edge of cclk and shifted out the dout on the negative edge of cclk. a parallel master mode device uses its internal timing generator to produce an internal cclk of eight times its eprom address rate, while a peripheral mode device produces a burst of eight cclks for each chip select and write- strobe cycle. the internal timing generator continues to operate for general timing and synchronization of inputs in all modes. figure 25. master mode with daisy-chained slave mode devices 5-3116(f) m0 m1 pwrdwn fpga +5 v hdc other rclk i/o pins general- purpose user i/o pins 5 k w m2 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 8 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 eprom oe ce d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d/p +5 v reset reprogram system open collector m0 m1 pwrdwn +5 v 5 k w hdc other ldc i/o pins general- purpose user i/o m2 init din cclk d/p reset dout m0 m1 pwrdwn +5 v 5 k w hdc other ldc i/o pins general- purpose user i/o m2 din cclk d/p reset dout fpga slave #1 fpga slave #n 5 k w each +5 v init reset cclk dout a15 a14 a13 a12 a11 master init ldc
lucent technologies inc. 27 data sheet february 1997 att3000 series field-programmable gate arrays special con?uration functions the con?uration data includes control over several special functions in addition to the normal user logic functions and interconnects: n input thresholds n readback enable n done pull-up resistor n done timing n reset timing n oscillator frequency divided by two each of these functions is controlled by con?uration data bits which are selected as part of the normal development system bit stream generation process. input thresholds prior to the completion of con?uration, all fpga input thresholds are ttl compatible. upon completion of con?uration, the input thresholds become either ttl or cmos compatible as programmed. the use of the ttl threshold option requires some additional supply current for threshold shifting. the exception is the threshold of the pwrd wn input and direct clocks which always have a cmos input. prior to the completion of con?uration, the user i/o pins each have a high- impedance pull-up. the con?uration program can be used to enable the iob pull-up resistors in the opera- tional mode to act either as an input load or to avoid a ?ating input on an otherwise unused pin. readback the contents of an fpga may be read back if it has been programmed with a bit stream in which the read- back option has been enabled. readback may be used for veri?ation of con?uration and as a method for determining the state of internal logic nodes. there are three options in generating the con?uration bit stream: n never will inhibit the readback capability. n one-time will inhibit readback after one readback has been executed to verify the con?uration. n on-command will allow unrestricted use of read- back. readback is accomplished without the use of any of the user i/o pins; only m0, m1, and cclk are used. the initiation of readback is produced by a low-to-high transition of the m0/rtrig (read trigger) pin. once the readback command has been given, the input cclk is driven by external logic to read back each data bit in a format similar to loading. after two dummy bits, the ?st data frame is shifted out on the m1/rdata (read data) pin. the logic polarity of the readback data is always inverted, such that a zero in con?uration becomes a one in readback and vice versa. each readback frame has one start bit and one stop bit per frame (con?ura- tion writes at least 3 stop bits per frame). all data frames must be read back to complete the process and return the mode select and cclk pins to their normal functions. the readback data includes the current state of each internal logic block storage element, and the state of the input (.i and .ri) connection pins on each iob. the data is imbedded into unused con?uration bit posi- tions during readback. this state information is used by the fpga development system in-circuit veri?r to pro- vide visibility into the internal operation of the logic while the system is operating. to read back a uniform time sample of all storage elements, it may be neces- sary to inhibit the system clock.
data sheet att3000 series field-programmable gate arrays february 1997 28 lucent technologies inc. special con?uration functions (continued) reprogram the fpga con?uration memory can be rewritten while the device is operating in the user? system. to initiate a reprogramming cycle, the dual-function pack- age pin done/ pr og must be given a high-to-low tran- sition. to reduce sensitivity to noise, the input signal is ?tered for two cycles of the fpga? internal timing gen- erator. when reprogram begins, the user-programma- ble i/o output buffers are disabled and high-impedance pull-ups are provided for the package pins. the device returns to the clear state and clears the con?uration memory before it prompts initialized . since this clear operation uses chip-individual internal timing, the master might complete the clear operation and then start con?uration before the slave has completed the clear operation. to avoid this, wire-and the slave init pins and use them to force a reset on the master (see figure 25). reprogram control is often implemented by using an external open-collector driver which pulls done/ pr og low. once it recognizes a stable request, the fpga will hold a low until the new con?uration has been completed. even if the reprogram request is externally held low beyond the con?uration period, the fpga will begin operation upon completion of con?u- ration. done pull-up done/ pr og is an open-drain i/o pin that indicates the fpga is in the operational state. an optional internal pull-up resistor can be enabled by the user of the devel- opment system when the bit stream generation pro- gram is executed. the done/ pr og pins of multiple fpgas in a daisy chain may be connected together to indicate that all are done or to direct them all to repro- gram. done timing the timing of the done status signal can be controlled by a selection in the bit stream generation program to occur a cclk cycle before, or after, the timing of out- puts being activated (see figure 20). this facilitates control of external functions, such as a prom enable or holding a system in a wait-state. reset timing as with done timing, the timing of the release of the internal reset can be controlled by a selection in the bit stream generation program to occur a cclk cycle before, or after, the timing of outputs being enabled (see figure 20). this reset maintains all user-program- mable ?p-?ps and latches in a zero state during con- ?uration. crystal oscillator division a selection in the bit stream generation program allows the user to incorporate a dedicated divide-by-two ?p- ?p in the crystal oscillator function. this provides higher assurance of a symmetrical timing signal. although the frequency stability of crystal oscillators is high, the symmetry of the waveform can be affected by bias or feedback drive.
data sheet february 1997 att3000 series field-programmable gate arrays lucent technologies inc. 29 performance device performance the high performance of the fpga is due in part to the manufacturing process, which is similar to that used for high-speed cmos static memories. performance can be measured in terms of minimum propagation times for logic elements. the parameter which traditionally describes the overall performance of a gate array is the toggle frequency of a ?p-?p. the con?uration for determining the toggle performance of the fpga is shown in figure 26. the ?p-?p output q is fed back through the combinatorial logic as q to form the toggle ?p-?p. figure 26. toggle flip-flop fpga performance is determined by the timing of critical paths, including both the ?ed timing for the logic and storage elements in that path, and the timing associated with the routing of the network. examples of internal worst-case timing are included in the performance data to allow the user to make the best use of the capabilities of the device. the orca foundry development system timing calculator or orca foundry-generated simulation models should be used to calculate worst-case paths by using actual impedance and loading information. figure 27 shows a variety of elements which are involved in determining system performance. table 20 gives the parameter values for the different speed grades. actual measurement of internal timing is not practical, and often only the sum of component timing is relevant as in the case of input to output. the relationship between input and output timing is arbi- trary, and only the total determines performance. timing components of internal functions may be deter- mined by the measurement of differences at the pins of the package. a synchronous logic function which involves a clock to block-output and a block-input to clock setup is capable of higher-speed operation than a logic con?uration of two synchronous blocks with an extra combinatorial block level between them. system clock rates to 60% of the toggle frequency are practical for logic in which an extra combinatorial level is located between synchronized blocks. this allows implementa- tion of functions of up to 25 variables. the use of the wired-and is also available for wide, high-speed functions. clock d q 5-3117(f) figure 27. examples of primary block speed factors clock logic logic clb clb clb (k) (k) iob pad t cko t ilo t ick t op clock to output combinatorial setup iob t pid t okop t cko pad 5-3118(f)
data sheet att3000 series field-programmable gate arrays february 1997 30 lucent technologies inc. performance (continued) logic block performance logic block performance is expressed as the propaga- tion time from the interconnect point at the input of the combinatorial logic to the output of the block in the interconnect area. combinatorial performance is inde- pendent of the speci? logic function because of the table look-up based implementation. timing is different when the combinatorial logic is used in conjunction with the storage element. for the combinatorial logic func- tion driving the data input of the storage element, the critical timing is data setup relative to the clock edge provided to the ?p-?p element. the delay from the clock source to the output of the logic block is critical in the timing of signals produced by storage elements. loading of a logic block output is limited only by the resulting propagation delay of the larger interconnect network. speed performance of the logic block is a function of supply voltage and temperature (see figures 28 and 29). interconnect performance interconnect performance depends on the routing resource used to implement the signal path. as dis- cussed earlier, direct interconnect from block to block provides a fast path for a signal. the single metal segment used for long lines exhibits low resistance from end to end, but relatively high capacitance. signals driven through a programmable switch will have the additional impedance of the switch added to their normal drive impedance. general-purpose interconnect performance depends on the number of switches and segments used, the presence of the bidirectional repowering buffers, and the overall loading on the signal path at all points along the path. in calculating the worst-case timing for a general interconnect path, the timing calculator portion of the orca foundry development system accounts for all of these elements. as an approximation, interconnect timing is propor- tional to the summation of totals of local metal seg- ments beyond each programmable switch. in effect, the time is a sum of r-c time each approximated by an r times the total c it drives. the r of the switch and the c of the interconnect are functions of the particular device performance grade. for a string of three local interconnects, the approxi- mate time at the ?st segment after the ?st switch resistance would be three units?n additional two units after the next switch plus an additional unit after the last switch in the chain. the interconnect r-c chain terminates at each repowering buffer. the capacitance of the actual block inputs is not signi?ant; the capaci- tance is in the interconnect metal and switches. figure 30 illustrates this.
data sheet february 1997 att3000 series field-programmable gate arrays lucent technologies inc. 31 performance (continued) figure 28. change in speed performance figure 29. speed performance of a cmos device 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.5 0.6 ?5 ?0 0 30 70 85 125 temperature (?) 5-3119(f) 1.2 1.1 1.0 0.9 4.0 4.5 5.0 5.5 6.0 v cc 5-3120(f) figure 30. interconnection timing example clb r1 timing: incremental if r1 = r2 = r3 = r and c1 = c2 = c3 = c, then cumulative timing r1(c1 + c2 + c3) t1 = 3rc = 3rc + r2(c2 + c3) t2 = 3rc + 2rc = 5rc + r3 + c3 t3 = 3rc + 2rc + rc = 6rc 6rc + buffer c1 c2 c3 c4 repowering buffer r2 r3 switch matrix 5-3121(f)
data sheet att3000 series field-programmable gate arrays february 1997 32 lucent technologies inc. power power distribution power for the fpga is distributed through a grid to achieve high noise immunity and isolation between logic and i/o. inside the fpga, a dedicated v cc and ground ring surrounding the logic array provides power to the i/o drivers (see figure 31 below). an indepen- dent matrix of v cc and ground lines supplies the inte- rior logic of the device. this power distribution grid provides a stable supply and ground for all internal logic, provided that the external package power pins are all connected and appropriately decoupled. typi- cally, a 0.1 ? capacitor connected near the v cc and ground pins of the package will provide adequate decoupling. output buffers which drive the speci?d 4 ma loads under worst-case conditions may drive 25 to 30 times this amount under best-case process conditions. noise can be reduced by minimizing external load capaci- tance and reducing simultaneous output transitions in the same direction. it may also be bene?ial to locate heavily loaded output buffers near the ground pads. the iob output buffers have a slew-limited mode which should be used where output rise and fall times are not speed critical. slew-limited outputs maintain their dc drive capability but generate less external re?ctions and internal noise. more than 32 fast outputs should not be switch- ing in the same direction simultaneously. figure 31. fpga power distribution v cc v cc gnd gnd ground and v cc ring for i/o drivers logic power grid 5-3122(f)
lucent technologies inc. 33 data sheet february 1997 att3000 series field-programmable gate arrays power (continued) power dissipation the fpga exhibits the low power consumption charac- teristic of cmos ics. the con?uration option of ttl chip input threshold requires power for the threshold reference. the power required by the static memory cells that hold the con?uration data is very low and may be maintained in a powerdown mode. typically, most of the power dissipation is produced by external capacitive loads on the output buffers. this load and frequency dependent power is 25 ?/pf/mhz per output. another component of i/o power is the dc loading on each output pin by devices driven by the fpga. internal power dissipation is a function of the number and size of the nodes, and the frequency at which they change. in an fpga, the fraction of nodes changing on a given clock is typically low (10% to 20%). for example, in a large binary counter, the average clock cycle produces changes equal to one clb output at the clock frequency. typical global clock buffer power is between 1.7 mw/mhz for the att3020 and 3.5 mw/ mhz for the att3090. the internal capacitive load is more a function of interconnect than fan-out. with a typical load of three general interconnect segments, each con?urable logic block output requires about 0.22 mw/mhz of its output frequency: total power = v cc + i cco + external (dc + capacitive) + internal (clb + iob + long line + pull-up) because the control storage of the fpga is cmos static memory, its cells require a very low standby cur- rent for data retention. in some systems, this low data retention current characteristic can be used as a method of preserving con?urations in the event of a primary power loss. the fpga has built-in powerdown logic which, when activated, will disable normal opera- tion of the device and retain only the con?uration data. all internal operation is suspended and output buffers are placed in their high-impedance state with no pull- ups. powerdown data retention is possible with a sim- ple battery backup circuit, because the power require- ment is extremely low. for retention at 2.4 v, the required current is typically on the order of 50 na. to force the fpga into the powerdown state, the user must pull the pwrd wn pin low and continue to supply a retention voltage to the v cc pins of the package. when normal power is restored, v cc is elevated to its normal operating voltage and pwrd wn is returned to a high. the fpga resumes operation with the same internal sequence that occurs at the conclusion of con?uration. internal i/o and logic block storage ele- ments will be reset, the outputs will become enabled, and the done/ pr og pin will be released. no con?u- ration programming is involved. when the power supply is removed from a cmos device, it is possible to supply some power from an input signal. the conventional electrostatic input pro- tection is implemented with diodes to the supply and ground. a positive voltage applied to an i/o will cause the positive protection diode to conduct and drive the power pin. this condition can produce invalid power conditions and should be avoided. a large series resis- tor might be used to limit the current or a bipolar buffer may be used to isolate the input signal.
data sheet att3000 series field-programmable gate arrays february 1997 34 lucent technologies inc. pin information table 4. permanently dedicated pins symbol name/description v cc two to eight (depending on package type) connections to the nominal +5 v supply voltage. all must be connected. gnd two to eight (depending on package type) connections to ground. all must be connected. pwrd wn a low on this cmos compatible input stops all internal activity to minimize v cc power, and puts all output buffers in a high-impedance state; con?uration is retained. when the pwrd wn pin returns high, the device returns to operation with the same sequence of buffer enable and done/ pr og as at the completion of con?uration. all internal storage elements are reset. if not used, pwrd wn must be tied to v cc . reset this is an active-low input which has three functions: n prior to the start of con?uration, a low input will delay the start of the con?uration process. an internal circuit senses the application of power and begins a minimal time-out cycle. when the time-out and reset are complete, the levels of the m lines are sampled and con?uration begins. n if reset is asserted during a con?uration, the fpga is reinitialized and will restart the con- ?uration at the termination of reset . n if reset is asserted after con?uration is complete, it will provide an asynchronous reset of all iob and clb storage elements of the fpga. cclk con?uration clock . during con?uration, this is an output of an fpga in master mode or peripheral mode. fpgas in slave mode use it as a clock input. during a readback operation, it is a clock input for the con?uration data being ?tered out. done/ pr og done output . con?urable as open drain with or without an internal pull-up resistor. at the completion of con?uration, the circuitry of the fpga becomes active in a synchronous order, and done may be programmed to occur one cycle before or after that occurs. once con?ura- tion is done, a high-to-low transition of this pin will cause an initialization of the fpga and start a recon?uration. m0/rtrig mode 0 . this input, m1, and m2 are sampled before the start of con?uration to establish the con?uration mode to be used. after con?uration is complete, a low-to-high transition acts as a read trigger to initiate a readback of con?uration and storage-element data clocked by cclk. m1/ rd a t a mode 1 . this input, m0, and m2 are sampled before the start of con?uration to establish the con?uration mode to be used. after con?uration is complete, this pin is the active-low output of the readback data.
data sheet february 1997 att3000 series field-programmable gate arrays lucent technologies inc. 35 pin information (continued) table 5. i/o pins with special functions symbol name/description m2 mode 2 . this input has a passive pull-up during con?uration. together with m0 and m1, it is sampled before the start of con?uration to establish the con?uration mode to be used. after con?uration, this pin becomes a user-programmable i/o pin. hdc high during con?uration . hdc is held at a high level by the fpga until after con?uration. it is available as a control output indicating that con?uration is not yet completed. after con?uration, this pin is a user i/o pin. ldc low during con?uration . this active-low signal is held at a low level by the fpga until after con?uration. it is available as a control output indicating that con?uration is not yet completed. it is particularly useful in master mode as a low enable for an eprom. after con?uration, this pin is a user i/o pin. if used as a low eprom enable, it must be programmed as a high after con?uration. init this is an active-low, open-drain output which is held low during the power stabilization and internal clearing of the con?uration memory. it can be used to indicate status to a con?uring microprocessor or, as a wired-and of several slave mode devices, a hold-off signal for a master mode device. after con?uration, this pin becomes a user-programmable i/o pin. bclkin this is a direct cmos level input to the alternate clock buffer (auxiliary buffer) in the lower right corner. xtl1 this user i/o pin can be used to operate as the output of an ampli?r driving an external crystal and bias circuitry. xtl2 this user i/o pin can be used as the input of an ampli?r connected to an external crystal and bias circuitry. the i/o block is left uncon?ured. the oscillator con?uration is activated by routing a net from the oscillator buffer symbol output and by the orca foundry bit stream generation program. cs0 , cs1 , cs2, ws these four inputs represent a set of signals, three active-low and one active-high, which are used in the peripheral mode to control con?uration data entry. the assertion of all four generates a write to the internal data buffer. the removal of any assertion clocks in the d[7:0] data present. in the master parallel mode, ws and cs2 are the a0 and a1 outputs. after con?uration, the pins are user-programmable i/o pins.
data sheet att3000 series field-programmable gate arrays february 1997 36 lucent technologies inc. rclk during master parallel mode con?uration, rclk represents a read of an external dynamic memory device (normally not used). rdy/ b usy during peripheral parallel mode con?uration, this pin indicates when the chip is ready for another byte of data to be written to it. after con?uration is complete, this pin becomes a user- programmed i/o pin. d[7:0] this set of eight pins represents the parallel con?uration byte for the parallel master and peripheral modes. after con?uration is complete, they are user-programmed i/o pins. a[15:0] this set of 16 pins presents an address output for a con?uration eprom during master parallel mode. after con?uration is complete, they are user-programmed i/o pins. din this user i/o pin is used as serial data input during slave or master serial con?uration. this pin is data zero input in master or peripheral con?uration mode. dout this user i/o pin is used during con?uration to output serial con?uration data for daisy- chained slaves?data in. tclkin this is a direct cmos level input to the global clock buffer. i/o input/output (unrestricted) . may be programmed by the user to be input and/or output pin following con?uration. some of these pins present a high-impedance pull-up (see next page) or perform other functions before con?uration is complete (see above). pin information (continued) table 5. i/o pins with special functions (continued) symbol name/description
data sheet february 1997 att3000 series field-programmable gate arrays lucent technologies inc. 37 pin information (continued) table 6a. att3000 family con?uration (44, 68, and 84 plcc; 100 qfp; and 100 tqfp) con?uration mode (m2:m1:m0) 44 plcc * 68 plcc 84 plcc ? 100 qfp 100 tqfp user operation slave (1:1:1) master-serial (0:0:0) peripheral (1:0:1) master-high (1:1:0) master-low (1:0:0) pwrdwn pwrdwn pwrdwn pwrdwn pwrdwn 7 10 12 29 26 pwrdwn v cc v cc v cc v cc v cc 12 18 22 41 38 v cc m1 (high) m1 (low) m1 (low) m1 (high) m1 (low) 16 25 31 52 49 rdata m0 (high) m0 (low) m0 (low) m0 (high) m0 (low) 17 26 32 54 51 rtrig m2 (high) m2 (low) m2 (high) m2 (high) m2 (low) 18 27 33 56 53 i/o hdc (high) hdc (high) hdc (high) hdc (high) hdc (high) 19 28 34 57 54 i/o ldc (low) ldc (low) ldc (low) ldc (low) ldc (low) 20 30 36 59 56 i/o init init init init init 22 34 42 65 62 i/o gnd gnd gnd gnd gnd 23 35 43 66 63 gnd 26 43 53 76 73 xtl2?/o reset reset reset reset reset 27 44 54 78 75 reset done done done done done 28 45 55 80 77 prog d7 d7 d7 46 56 81 78 i/o 30 47 57 82 79 xtl1?/o d6 d6 d6 48 58 83 80 i/o d5 d5 d5 49 60 87 84 i/o cs0 50 61 88 85 i/o d4 d4 d4 51 62 89 86 i/o v cc v cc v cc v cc v cc 34 52 64 91 88 v cc d3 d3 d3 53 65 92 89 i/o cs1 54 66 93 90 i/o d2 d2 d2 55 67 94 91 i/o d1 d1 d1 56 70 98 95 i/o rdy/ busy rclk rclk 57 71 99 96 i/o din din d0 d0 d0 38 58 72 100 97 i/o dout dout dout dout dout 39 59 73 1 98 i/o cclk cclk cclk cclk cclk 40 60 74 2 99 cclk ws a0 a0 61 75 5 2 i/o cs2 a1 a1 62 76 6 3 i/o a2 a2 63 77 8 5 i/o a3 a3 64 78 9 6 i/o a15 a15 65 81 12 9 i/o a4 a4 66 82 13 10 i/o a14 a14 67 83 14 11 i/o a5 a5 68 84 15 12 i/o gnd gnd gnd gnd gnd 1 1 1 16 13 gnd a13 a13 2 2 17 14 i/o a6 a6 3 3 18 15 i/o a12 a12 4 4 19 16 i/o a7 a7 5 5 20 17 i/o a11 a11 6 8 23 20 i/o a8 a8 7 9 24 21 i/o a10 a10 8 10 25 22 i/o a9 a9 9 11 26 23 i/o represents a 50 k w to 100 k w pull-up. * peripheral mode and master parallel mode are not supported in the 44-pin plcc package; see table 7. ? pin assignments for the att3064/att3090 differ from those shown; see page 42. ? init is an open-drain output during configuration.
data sheet att3000 series field-programmable gate arrays february 1997 38 lucent technologies inc. pin information (continued) table 6b. att3000 family con?uration (132 ppga, 144 tqfp, 160 qfp, 175 ppga, 208 sqfp) con?uration mode (m2:m1:m0) 132 ppga 144 tqfp 160 qfp 175 ppga 208 sqfp user operation slave (1:1:1) master-serial (0:0:0) peripheral (1:0:1) master-high (1:1:0) master-low (1:0:0) pwrdwn pwrdwn pwrdwn pwrdwn pwrdwn a1 1 159 b2 3 pwrdwn v cc v cc v cc v cc v cc c8 19 20 d9 26 v cc m1 (high) m1 (low) m1 (low) m1 (high) m1 (low) b13 36 40 b14 48 rdata m0 (high) m0 (low) m0 (low) m0 (high) m0 (low) a14 38 42 b15 50 rtrig m2 (high) m2 (low) m2 (high) m2 (high) m2 (low) c13 40 44 c15 56 i/o hdc (high) hdc (high) hdc (high) hdc (high) hdc (high) b14 41 45 e14 57 i/o ldc (low) ldc (low) ldc (low) ldc (low) ldc (low) d14 45 49 d16 61 i/o init* init* init* init* init* g14 53 59 h15 77 i/o gnd gnd gnd gnd gnd h12 55 19 j14 25 gnd m13 69 76 p15 100 xtl2?/o reset reset reset reset reset p14 71 78 r15 102 reset done done done done done n13 73 80 r14 107 prog d7 d7 d7 m12 74 81 n13 109 i/o p13 75 82 t14 110 xtl1?/o d6 d6 d6 n11 78 86 p12 115 i/o d5 d5 d5 m9 84 92 t11 122 i/o cs0 n9 85 93 r10 123 i/o d4 d4 d4 n8 88 98 r9 128 i/o v cc v cc v cc v cc v cc m8 90 100 n9 130 v cc d3 d3 d3 n7 92 102 p8 132 i/o cs1 p6 93 103 r8 133 i/o d2 d2 d2 m6 96 108 r7 138 i/o d1 d1 d1 m5 102 114 r5 145 i/o rdy/ busy rclk rclk n4 103 115 p5 146 i/o din din d0 d0 d0 n2 106 119 r3 151 i/o dout dout dout dout dout m3 107 120 n4 152 i/o cclk cclk cclk cclk cclk p1 108 121 r2 153 cclk ws a0 a0 m2 111 124 p2 161 i/o cs2 a1 a1 n1 112 125 m3 162 i/o a2 a2 l2 115 128 p1 165 i/o a3 a3 l1 116 129 n1 166 i/o a15 a15 k1 119 132 m1 172 i/o a4 a4 j2 120 133 l2 173 i/o a14 a14 h1 123 136 k2 178 i/o a5 a5 h2 124 137 k1 179 i/o gnd gnd gnd gnd gnd h3 126 139 j3 182 gnd a13 a13 g2 128 141 h2 184 i/o a6 a6 g1 129 142 h1 185 i/o a12 a12 f2 133 147 f2 192 i/o a7 a7 e1 134 148 e1 193 i/o a11 a11 d1 137 151 d1 199 i/o a8 a8 d2 138 152 c1 200 i/o a10 a10 b1 141 155 e3 203 i/o a9 a9 c2 142 156 c2 204 i/o represents a 50 k w to 100 k w pull-up. * init is an open-drain output during configuration.
data sheet february 1997 att3000 series field-programmable gate arrays lucent technologies inc. 39 pin assignments notes: peripheral mode and master parallel mode are not supported in the m44 package. parallel address and data pins are not assigned. table 7. att3030 44-pin plcc pinout pin no. function pin no. function 1 gnd 23 gnd 2 i/o 24 i/o 3 i/o 25 i/o 4 i/o 26 xtl2?/o 5 i/o 27 reset 6 i/o 28 done pr og 7 pwrd wn 29 i/o 8 tclkin?/o 30 xtl1?clkin?/o 9 i/o 31 i/o 10 i/o 32 i/o 11 i/o 33 i/o 12 v cc 34 v cc 13 i/o 35 i/o 14 i/o 36 i/o 15 i/o 37 i/o 16 m1 rd a t a 38 din?/o 17 m0?trig 39 dout?/o 18 m2?/o 40 cclk 19 hdc?/o 41 i/o 20 ldc ?/o 42 i/o 21 i/o 43 i/o 22 init ?/o 44 i/o
data sheet att3000 series field-programmable gate arrays february 1997 40 lucent technologies inc. pin assignments (continued) table 8. att3020, att3030, and att3042; 68-pin plcc and 84-pin plcc pinout * pin numbers function pin numbers function 68 plcc 84 plcc 68 plcc 84 plcc 10 12 pwrd wn 38 46 i/o 11 13 tclkin?/o 39 47 i/o 14 i/o ? 40 48 i/o 12 15 i/o 41 49 i/o 13 16 i/o 50 i/o ? 17 i/o 51 i/o ? 14 18 i/o 42 52 i/o 15 19 i/o 43 53 xtl2?/o 16 20 i/o 44 54 reset 17 21 i/o 45 55 done pr og 18 22 v cc 46 56 d7?/o 19 23 i/o 47 57 xtl1?clkin?/o 24 i/o 48 58 d6?/o 20 25 i/o 59 i/o 21 26 i/o 49 60 d5?/o 22 27 i/o 50 61 cs0 ?/o 28 i/o 51 62 d4?/o 23 29 i/o 63 i/o 24 30 i/o 52 64 v cc 25 31 m1 rd a t a 53 65 d3?/o 26 32 m0?trig 54 66 cs1 ?/o 27 33 m2?/o 55 67 d2?/o 28 34 hdc?/o 68 i/o 29 35 i/o 69 i/o ? 30 36 ldc ?/o 56 70 d1?/o 31 37 i/o 57 71 rdy/ b usy rclk ?/o 38 i/o ? 58 72 d0?in?/o 32 39 i/o 59 73 dout?/o 33 40 i/o 60 74 cclk 41 i/o ? 61 75 a0 ws ?/o 34 42 init ?/o 62 76 a1?s2?/o 35 43 gnd 63 77 a2?/o 36 44 i/o 64 78 a3?/o 37 45 i/o 79 i/o ? * unprogrammed iobs have a default pull-up; this prevents an unde?ed pad level for unbonded or unused iobs. programmed outputs are default slew-limited. ? indicates unconnected package pins for the att3020.
data sheet february 1997 att3000 series field-programmable gate arrays lucent technologies inc. 41 note: table 8 describes the pin assignments for three different chips in two different packages. the function column lists 84 of the 118 pads on the att3042 and 84 of the 98 pads on the att3030. ten pads [indicated with a dagger (?)] do not exist on the att3020, which has 74 pads; therefore, the corresponding pins on the 84-pin packages have no connections to an att3020. 80 i/o ? 4 4 a12?/o 65 81 a15?/o 5 5 a7?/o 66 82 a4?/o 6 i/o ? 67 83 a14?/o 7 i/o ? 68 84 a5?/o 6 8 a11?/o 1 1 gnd 7 9 a8?/o 2 2 a13?/o 8 10 a10?/o 3 3 a6?/o 9 11 a9?/o pin assignments (continued) table 8. att3020, att3030, and att3042; 68-pin plcc and 84-pin plcc pinout * (continued) pin numbers function pin numbers function 68 plcc 84 plcc 68 plcc 84 plcc * unprogrammed iobs have a default pull-up; this prevents an unde?ed pad level for unbonded or unused iobs. programmed outputs are default slew-limited. ? indicates unconnected package pins for the att3020.
data sheet att3000 series field-programmable gate arrays february 1997 42 lucent technologies inc. pin assignments (continued) * different pin de?ition than att3020/att3030/att3042 pc84 package. note: unprogrammed iobs have a default pull-up; this prevents an unde?ed pad level for unbonded or unused iobs. programmed outputs are default slew-limited. table 9. att3064 and att3090 84-pin plcc pinout 84 plcc function 84 plcc function 84 plcc function 12 pwrd wn 40 i/o 68 d2?/o* 13 tclkin?/o 41 init ?/o* 69 i/o 14 i/o 42 v cc * 70 d1?/o 15 i/o 43 gnd 71 rdy/ b usy rclk ?/o 16 i/o 44 i/o 72 d0?in?/o 17 i/o 45 i/o 73 dout?/o 18 i/o 46 i/o 74 cclk 19 i/o 47 i/o 75 a0 ws ?/o 20 i/o 48 i/o 76 a1?s2?/o 21 gnd* 49 i/o 77 a2?/o 22 v cc 50 i/o 78 a3?/o 23 i/o 51 i/o 79 i/o* 24 i/o 52 i/o 80 i/o* 25 i/o 53 xtl2?/o 81 a15?/o 26 i/o 54 reset 82 a4?/o 27 i/o 55 done pr og 83 a14?/o 28 i/o 56 d7?/o 84 a5?/o 29 i/o 57 xtl1?clkin?/o 1 gnd 30 i/o 58 d6?/o 2 v cc * 31 m1 rd a t a 59 i/o 3 a13?/o* 32 m0?trig 60 d5?/o 4 a6?/o* 33 m2?/o 61 cs0 ?/o 5 a12?/o* 34 hdc?/o 62 d4?/o 6 a7?/o* 35 i/o 63 i/o 7 i/o 36 ldc ?/o 64 v cc 8 a11?/o 37 i/o 65 gnd* 9 a8?/o 38 i/o 66 d3?/o* 10 a10?/o 39 i/o 67 cs1 ?/o* 11 a9?/o
data sheet february 1997 att3000 series field-programmable gate arrays lucent technologies inc. 43 pin assignments (continued) * only 100 of the 118 pads on the att3042 are connected to the 100 package pins. two pads, indicated by double asterisks, do not exist on the att3030, which has 98 pads; therefore, the corresponding pins have no connections. twenty-six pads, indicated by single or double asterisks, do not exist on the att3020, which has 74 pads; therefore, the corresponding pins have no connections. note: unprogrammed iobs have a default pull-up; this prevents an unde?ed pad level for unbonded or unused iobs. programmed outputs are default slew-limited. table 10. att3020, att3030, and att3042 100-pin qfp pinout 100 qfp function 100 qfp function 100 qfp function 16 gnd 50 i/o* 84 i/o* 17 a13?/o 51 i/o* 85 i/o* 18 a6?/o 52 m1 rd a t a 86 i/o 19 a12?/o 53 gnd* 87 d5?/o 20 a7?/o 54 m0?trig 88 cs0 ?/o 21 i/o* 55 v cc * 89 d4?/o 22 i/o* 56 m2?/o 90 i/o 23 a11?/o 57 hdc?/o 91 v cc 24 a8?/o 58 i/o 92 d3?/o 25 a10?/o 59 ldc ?/o 93 cs1 ?/o 26 a9?/o 60 i/o* 94 d2?/o 27* v cc 61 i/o* 95 i/o 28* gnd 62 i/o 96 i/o* 29 pwrd wn 63 i/o 97 i/o* 30 tclkin?/o 64 i/o 98 d1?/o 31 i/o** 65 init ?/o 99 rclk rdy/b usy ?/o 32 i/o* 66 gnd 100 d0?in?/o 33 i/o* 67 i/o 1 dout?/o 34 i/o 68 i/o 2 cclk 35 i/o 69 i/o 3 v cc * 36 i/o 70 i/o 4 gnd* 37 i/o 71 i/o 5 a0 ws ?/o 38 i/o 72 i/o 6 a1?s2?/o 39 i/o 73 i/o 7 i/o** 40 i/o 74 i/o* 8 a2?/o 41 v cc 75 i/o* 9 a3?/o 42 i/o 76 xtl2?/o 10 i/o* 43 i/o 77* gnd 11 i/o* 44 i/o 78 reset 12 a15?/o 45 i/o 79 v cc * 13 a4?/o 46 i/o 80 done pr og 14 a14?/o 47 i/o 81 d7?/o 15 a5?/o 48 i/o 82 xtl1?clkin?/o 49 i/o 83 d6?/o
data sheet att3000 series field-programmable gate arrays february 1997 44 lucent technologies inc. pin assignments (continued) * indicates unconnected package pins for the att3030. note: unprogrammed iobs have a default pull-up; this prevents an unde?ed pad level for unbonded or unused iobs. programmed outputs are default slew-limited. table 11. att3030, att3042, and att3064 100-pin tqfp pinout 100 tqfp function 100 tqfp function 100 tqfp function 13 gnd 47 i/o 81 i/o 14 a13?/o 48 i/o 82 i/o 15 a6?/o 49 m1 rd a t a 83 i/o 16 a12?/o 50 gnd 84 d5?/o 17 a7?/o 51 m0?trig 85 cs0 ?/o 18 i/o 52 v cc 86 d4?/o 19 i/o 53 m2?/o 87 i/o 20 a11?/o 54 hdc?/o 88 v cc 21 a8?/o 55 i/o 89 d3?/o 22 a10?/o 56 ldc ?/o 90 cs1 ?/o 23 a9?/o 57 i/o 91 d2?/o 24 v cc 58 i/o 92 i/o 25 gnd 59 i/o 93 i/o 26 pwrd wn 60 i/o 94 i/o 27 tclkin?/o 61 i/o 95 d1?/o 28 i/o* 62 init ?/o 96 rclk rdy/ b usy ?/o 29 i/o 63 gnd 97 d0?in?/o 30 i/o 64 i/o 98 dout?/o 31 i/o 65 i/o 99 cclk 32 i/o 66 i/o 100 v cc 33 i/o 67 i/o 1 gnd 34 i/o 68 i/o 2 a0 ws ?/o 35 i/o 69 i/o 3 a1?s2?/o 36 i/o 70 i/o 4 i/o* 37 i/o 71 i/o 5 a2?/o 38 v cc 72 i/o 6 a3?/o 39 i/o 73 xtl2?/o 7 i/o 40 i/o 74 gnd 8 i/o 41 i/o 75 reset 9 a15?/o 42 i/o 76 v cc 10 a4?/o 43 i/o 77 done pr og 11 a14?/o 44 i/o 78 d7?/o 12 a5?/o 45 i/o 79 xtl1?clkin?/o 46 i/o 80 d6?/o
data sheet february 1997 att3000 series field-programmable gate arrays lucent technologies inc. 45 pin assignments (continued) * indicates unconnected package pins for the att3030. note: unprogrammed iobs have a default pull-up; this prevents an unde?ed pad level for unbonded or unused iobs. programmed outputs are default slew-limited. table 12. att3042 and att3064 132-pin ppga pinout 132 ppga function 132 ppga function 132 ppga function c4 gnd f12 i/o n6 i/o* a1 pwrd wn e14 i/o p5 i/o* c3 tclkin?/o f13 i/o m6 d2?/o b2 i/o f14 i/o n5 i/o b3 i/o g13 i/o p4 i/o a2 i/o* g14 init ?/o p3 i/o b4 i/o g12 v cc m5 d1?/o c5 i/o h12 gnd n4 rclk ?dy/b usy ?/o a3 i/o* h14 i/o p2 i/o a4 i/o h13 i/o n3 i/o b5 i/o j14 i/o n2 d0?in?/o c6 i/o j13 i/o m3 dout?/o a5 i/o k14 i/o p1 cclk b6 i/o j12 i/o m4 v cc a6 i/o k13 i/o l3 gnd b7 i/o l14 i/o* m2 a0 ws ?/o c7 gnd l13 i/o n1 a1?s2?/o c8 v cc k12 i/o m1 i/o a7 i/o m14 i/o k3 i/o b8 i/o n14 i/o l2 a2?/o a8 i/o m13 xtl2?/o l1 a3?/o a9 i/o l12 gnd k2 i/o b9 i/o p14 reset j3 i/o c9 i/o m11 v cc k1 a15?/o a10 i/o n13 done pr og j2 a4?/o b10 i/o m12 d7?/o j1 i/o* a11 i/o* p13 xtl1?clkin?/o h1 a14?/o c10 i/o n12 i/o h2 a5?/o b11 i/o p12 i/o h3 gnd a12 i/o* n11 d6?/o g3 v cc b12 i/o m10 i/o g2 a13?/o a13 i/o* p11 i/o* g1 a6?/o c12 i/o n10 i/o f1 i/o* b13 m1 rd a t a p10 i/o f2 a12?/o c11 gnd m9 d5?/o e1 a7?/o a14 m0?trig n9 cs0 ?/o f3 i/o d12 v cc p9 i/o* e2 i/o c13 m2?/o p8 i/o* d1 a11?/o b14 hdc?/o n8 d4?/o d2 a8?/o c14 i/o p7 i/o e3 i/o e12 i/o m8 v cc c1 i/o d13 i/o m7 gnd b1 a10?/o d14 ldc ?/o n7 d3?/o c2 a9?/o e13 i/o* p6 cs1 ?/o d3 v cc
data sheet att3000 series field-programmable gate arrays february 1997 46 lucent technologies inc. pin assignments (continued) * indicates unconnected package pins for the att3042. note: unprogrammed iobs have a default pull-up; this prevents an unde?ed pad level for unbonded or unused iobs. programmed outputs are default slew-limited. table 13. att3042 and att3064 144-pin tqfp pinout 144 tqfp function 144 tqfp function 144 tqfp function 144 tqfp function 1 pwrd wn 37 gnd 73 done pr og 109 v cc 2 tclkin?/o 38 m0?trig 74 d7?/o 110 gnd 3 i/o* 39 v cc 75 xtl1?clkin?/o 111 a0 ws ?/o 4 i/o 40 m2?/o 76 i/o 112 a1?s2?/o 5 i/o 41 hdc?/o 77 i/o 113 i/o 6 i/o* 42 i/o 78 d6?/o 114 i/o 7 i/o 43 i/o 79 i/o 115 a2?/o 8 i/o 44 i/o 80 i/o* 116 a3?/o 9 i/o* 45 ldc ?/o 81 i/o 117 i/o 10 i/o 46 i/o* 82 i/o 118 i/o 11 i/o 47 i/o 83 i/o* 119 a15?/o 12 i/o 48 i/o 84 d5?/o 120 a4?/o 13 i/o 49 i/o 85 cs0 ?/o 121 i/o* 14 i/o 50 i/o* 86 i/o* 122 i/o* 15 i/o* 51 i/o 87 i/o* 123 a14 i/o 16 i/o 52 i/o 88 d4?/o 124 a5?/o 17 i/o 53 init ?/o 89 i/o 125 18 gnd 54 v cc 90 v cc 126 gnd 19 v cc 55 gnd 91 gnd 127 v cc 20 i/o 56 i/o 92 d3?/o 128 a13?/o 21 i/o 57 i/o 93 cs1 ?/o 129 a6?/o 22 i/o 58 i/o 94 i/o* 130 i/o* 23 i/o 59 i/o 95 i/o* 131 24 i/o 60 i/o 96 d2?/o 132 i/o* 25 i/o 61 i/o 97 i/o 133 a12?/o 26 i/o 62 i/o 98 i/o 134 a7?/o 27 i/o 63 i/o* 99 i/o* 135 i/o 28 i/o* 64 i/o* 100 i/o 136 i/o 29 i/o 65 i/o 101 i/o* 137 a11?/o 30 i/o 66 i/o 102 d1?/o 138 a8?/o 31 i/o* 67 i/o 103 rclk ? usy /rdy?/o 139 i/o 32 i/o* 68 i/o 104 i/o 140 i/o 33 i/o 69 xtl2?/o 105 i/o 141 a10?/o 34 i/o* 70 gnd 106 d0?in?/o 142 a9?/o 35 i/o 71 reset 107 dout?/o 143 v cc 36 m1 rd a t a 72 v cc 108 cclk 144 gnd
data sheet february 1997 att3000 series field-programmable gate arrays lucent technologies inc. 47 pin assignments (continued) * indicates unconnected package pins for the att3064. note: unprogrammed iobs have a default pull-up; this prevents an unde?ed pad level for unbonded or unused iobs. programmed outputs are default slew-limited. table 14. att3064 and att3090 160-pin qfp pinout 160 qfp function 160 qfp function 160 qfp function 160 qfp function 1 i/o* 41 gnd 81 d7?/o 121 cclk 2 i/o* 42 m0?trig 82 xtl1?clkin?/o 122 v cc 3 i/o* 43 v cc 83 i/o* 123 gnd 4 i/o 44 m2?/o 84 i/o 124 a0 ws ?/o 5 i/o 45 hdc?/o 85 i/o 125 a1?s2?/o 6 i/o 46 i/o 86 d6?/o 126 i/o 7 i/o 47 i/o 87 i/o 127 i/o 8 i/o 48 i/o 88 i/o 128 a2?/o 9 i/o 49 ldc ?/o 89 i/o 129 a3?/o 10 i/o 50 i/o* 90 i/o 130 i/o 11 i/o 51 i/o* 91 i/o 131 i/o 12 i/o 52 i/o 92 d5?/o 132 a15?/o 13 i/o 53 i/o 93 cs0 i/o 133 a4?/o 14 i/o 54 i/o 94 i/o* 134 i/o 15 i/o 55 i/o 95 i/o* 135 i/o 16 i/o 56 i/o 96 i/o 136 a14 i/o 17 i/o 57 i/o 97 i/o 137 a5?/o 18 i/o 58 i/o 98 d4?/o 138 i/o* 19 gnd 59 init ?/o 99 i/o 139 gnd 20 v cc 60 v cc 100 v cc 140 v cc 21 i/o* 61 gnd 101 gnd 141 a13?/o 22 i/o 62 i/o 102 d3?/o 142 a6?/o 23 i/o 63 i/o 103 cs1 ?/o 143 i/o* 24 i/o 64 i/o 104 i/o 144 i/o* 25 i/o 65 i/o 105 i/o 145 i/o 26 i/o 66 i/o 106 i/o* 146 i/o 27 i/o 67 i/o 107 i/o* 147 a12?/o 28 i/o 68 i/o 108 d2?/o 148 a7?/o 29 i/o 69 i/o 109 i/o 149 i/o 30 i/o 70 i/o 110 i/o 150 i/o 31 i/o 71 i/o 111 i/o 151 a11?/o 32 i/o 72 i/o 112 i/o 152 a8?/o 33 i/o 73 i/o 113 i/o 153 i/o 34 i/o 74 i/o 114 d1?/o 154 i/o 35 i/o 75 i/o* 115 rclk rdy/b usy ?/o 155 a10?/o 36 i/o 76 xtl2?/o 116 i/o 156 a9?/o 37 i/o 77 gnd 117 i/o 157 v cc 38 i/o * 78 reset 118 i/o * 158 gnd 39 i/o * 79 v cc 119 d0?in?/o 159 pwrd wn 40 m1 rd a t a 80 done pr og 120 dout?/o 160 tclkin?/o
data sheet att3000 series field-programmable gate arrays february 1997 48 lucent technologies inc. pin assignments (continued) table 15. att3000 family 175-pin ppga pinout 175 ppga function 175 ppga function 175 ppga function 175 ppga function b2 pwrd wn d13 i/o r14 done pr og r3 d0?in?/o d4 tclkin?/o b14 m1 rd a t a n13 d7?/o n4 dout?/o b3 i/o c14 gnd t14 xtl1?clkin?/o r2 cclk c4 i/o b15 m0?trig p13 i/o p3 v cc b4 i/o d14 v cc r13 i/o n3 gnd a4 i/o c15 m2?/o t13 i/o p2 a0 ws ?/o d5 i/o e14 hdc?/o n12 i/o m3 a1?s2?/o c5 i/o b16 i/o p12 d6?/o r1 i/o b5 i/o d15 i/o r12 i/o n2 i/o a5 i/o c16 i/o t12 i/o p1 a2?/o c6 i/o d16 ldc ?/o p11 i/o n1 a3?/o d6 i/o f14 i/o n11 i/o l3 i/o b6 i/o e15 i/o r11 i/o m2 i/o a6 i/o e16 i/o t11 d5?/o m1 a15 i/o b7 i/o f15 i/o r10 cs0 ?/o l2 a4?/o c7 i/o f16 i/o p10 i/o l1 i/o d7 i/o g14 i/o n10 i/o k3 i/o a7 i/o g15 i/o t10 i/o k2 a14?/o a8 i/o g16 i/o t9 i/o k1 a5?/o b8 i/o h16 i/o r9 d4?/o j1 i/o c8 i/o h15 init ?/o p9 i/o j2 i/o d8 gnd h14 v cc n9 v cc j3 gnd d9 v cc j14 gnd n8 gnd h3 v cc c9 i/o j15 i/o p8 d3?/o h2 a13?/o b9 i/o j16 i/o r8 cs1 ?/o h1 a6?/o a9 i/o k16 i/o t8 i/o g1 i/o a10 i/o k15 i/o t7 i/o g2 i/o d10 i/o k14 i/o n7 i/o g3 i/o c10 i/o l16 i/o p7 i/o f1 i/o b10 i/o l15 i/o r7 d2?/o f2 a12?/o a11 i/o m16 i/o t6 i/o e1 a7?/o b11 i/o m15 i/o r6 i/o e2 i/o d11 i/o l14 i/o n6 i/o f3 i/o c11 i/o n16 i/o p6 i/o d1 a11?/o a12 i/o p16 i/o t5 i/o c1 a8?/o b12 i/o n15 i/o r5 d1?/o d2 i/o c12 i/o r16 i/o p5 rdy / b usy rclk ?/o b1 i/o d12 i/o m14 i/o n5 i/o e3 a10?/o a13 i/o p15 xtl2?/o t4 i/o c2 a9?/o b13 i/o n14 gnd r4 i/o d3 v cc c13 i/o r15 reset p4 i/o c3 gnd a14 i/o p14 v cc note:unprogrammed iobs have a default pull-up; this prevents an unde?ed pad level for unbonded or unused iobs. programmed outputs are default slew-limited. pins a2, a3, a15, a16, t1, t2, t3, t15, and t16 are not connected. pin a1 does not exist.
data sheet february 1997 att3000 series field-programmable gate arrays lucent technologies inc. 49 pin assignments (continued) note: unprogrammed iobs have a default pull-up; this prevents an unde?ed pad level for unbonded or unused iobs. programmed outputs are default slew-limited. table 16. att3000 family 208-pin sqfp pinout 208 sqfp function 208 sqfp function 208 sqfp function 208 sqfp function 1 53 105 157 2 gnd 54 106 v cc 158 3 pwrd wn 55 v cc 107 done pr og 159 4 tclkin?/o 56 m2?/o 108 160 gnd 5 i/o 57 hdc?/o 109 d7?/o 161 a0 ws ?/o 6 i/o 58 i/o 110 xtl1?clkin?/o 162 a1?s2?/o 7 i/o 59 i/o 111 i/o 163 i/o 8 i/o 60 i/o 112 i/o 164 i/o 9 i/o 61 ldc ?/o 113 i/o 165 a2?/o 10 i/o 62 i/o 114 i/o 166 a3?/o 11 i/o 63 i/o 115 d6?/o 167 i/o 12 i/o 64 116 i/o 168 i/o 13 i/o 65 117 i/o 169 14 i/o 66 118 i/o 170 15 i/o 67 119 171 16 i/o 68 i/o 120 i/o 172 a15?/o 17 i/o 69 i/o 121 i/o 173 a4?/o 18 i/o 70 i/o 122 d5?/o 174 i/o 19 i/o 71 i/o 123 cs0 ?/o 175 i/o 20 i/o 72 124 i/o 176 21 i/o 73 125 i/o 177 22 i/o 74 i/o 126 i/o 178 a14?/o 23 i/o 75 i/o 127 i/o 179 a5?/o 24 i/o 76 i/o 128 d4?/o 180 i/o 25 gnd 77 init ?/o 129 i/o 181 i/o 26 v cc 78 v cc 130 v cc 182 gnd 27 i/o 79 gnd 131 gnd 183 v cc 28 i/o 80 i/o 132 d3?/o 184 a13?/o 29 i/o 81 i/o 133 cs1 ?/o 185 a6?/o 30 i/o 82 i/o 134 i/o 186 i/o 31 i/o 83 135 i/o 187 i/o 32 i/o 84 136 i/o 188 33 i/o 85 i/o 137 i/o 189 34 i/o 86 i/o 138 d2?/o 190 i/o 35 i/o 87 i/o 139 i/o 191 i/o 36 i/o 88 i/o 140 i/o 192 a12?/o 37 89 i/o 141 i/o 193 a7?/o 38 i/o 90 142 194 39 i/o 91 143 i/o 195 40 i/o 92 144 i/o 196 41 i/o 93 i/o 145 d1?/o 197 i/o 42 i/o 94 i/o 146 rdy/b usy rclk ?/o 198 i/o 43 i/o 95 i/o 147 i/o 199 a11?/o 44 i/o 96 i/o 148 i/o 200 a8?/o 45 i/o 97 i/o 149 i/o 201 i/o 46 i/o 98 i/o 150 i/o 202 i/o 47 i/o 99 i/o 151 d0?in?/o 203 a10?/o 48 m1 rd a t a 100 xtl2?/o 152 dout?/o 204 a9?/o 49 gnd 101 gnd 153 cclk 205 v cc 50 m0?trig 102 reset 154 v cc 206 51 103 155 207 52 104 156 208
data sheet att3000 series field-programmable gate arrays february 1997 50 lucent technologies inc. package thermal characteristics when silicon die junction temperature is below the rec- ommended junction temperature of 125 ?, the temperature-activated failure mechanisms are mini- mized. there are four major factors that affect the ther- mal resistance value: silicon device size/paddle size, board-mounting con?uration (board density, multilayer nature of board), package type and size, and system air?w over the package. the values in the table below re?ct the capability of the various package types to dissipate heat at given air?w rates. the numbers rep- resent the delta ?/w between the ambient tempera- ture and the device junction temperature. to test package thermal characteristics, a single pack- age containing a 0.269 in. sq. test ic of each con?ura- tion is mounted at the center of a printed-circuit board (pcb) measuring 8 in. x 13 in. x 0.062 in. the assem- bled pcb is mounted vertically in the center of the rect- angular test section of a wind tunnel. the walls of the wind tunnel simulate adjacent boards in the electronic rack and can be adjusted to study the effects of pcb spacing. forced air at room temperature is supplied by a pair of push-pull blowers which can be regulated to supply the desired air velocities. the air velocity is measured with a hot-wire anemometer at the center of the channel, 3 in. upstream from the package. a typical test consists of regulating the wind tunnel blowers to obtain the desired air velocity and applying power to the test ic. the power to the ic is adjusted until the maximum junction temperature (as measured by its diodes) reaches 115 ? to 120 ?. the thermal resistance q ja (?/w) is computed by using the power supplied to the ic, junction temperature, ambient tem- perature, and air velocity: where: t j = peak temperature on the active surface of the ic t a = ambient air temperature q c = ic power the tests are repeated at several velocities from 0 fpm (feet per minute) to 1000 fpm. the de?ition of the junction to case thermal resistance q jc is: where: t c = temperature measured to the thermocouple at the top dead center of the package the actual q jc measurement performed at lucent, q j ?tdc , uses a different package mounting arrange- ment than the one de?ed for q jc in mil-std-883d and semi standards. please contact lucent for a dia- gram. the maximum power dissipation for a package is cal- culated from the maximum junction temperature, maxi- mum operating temperature, and the junction to ambient characteristic q ja . the maximum power dissi- pation for commercial grade ics is calculated as fol- lows: max power (watts) = (125 ? ?70 ?) x (1/ q ja ), where 125 ? is the maximum junction temperature. table 17 lists the att3000 plastic package thermal characteristics. q ja t j t a q c ------------------- - = q jc t j t c q c ------------------- - =
data sheet february 1997 att3000 series field-programmable gate arrays lucent technologies inc. 51 package thermal characteristics (continued) table 17. att3000 plastic package thermal characteristics package q ja (?/w) q jc (?/w) max power (70 ?? fpm) 0 fpm 200 fpm 400 fpm 44-pin plcc 49 43 40 1.12 w 68-pin plcc 43 38 35 11 1.28 w 84-pin plcc 40 35 32 9 1.38 w 100-pin qfp 81 67 64 11 0.68 w 100-pin tqfp 61 49 46 6 0.90 w 132-pin ppga 22 18 16 2.50 w 144-pin tqfp 52 39 36 4 1.06 w 160-pin qfp 40 36 32 8 1.38 w 175-pin ppga 23 20 17 2.39 w 208-pin sqfp 37 33 29 8 1.49 w package coplanarity the coplanarity of lucent technologies postmolded packages is 4 mils. the coplanarity of the sqfp and tqfp packages is 3.15 mils. package parasitics the electrical performance of an ic package, such as signal quality and noise sensitivity, is directly affected by the package parasitics. table 18 lists eight parasitics associated with the att3000 packages. these parasit- ics represent the contributions of all components of a package, which include the bond wires, all internal package routing, and the external leads. four inductances in nh are listed: l w and l l, the self- inductance of the lead; and l mw and l ml , the mutual inductance to the nearest neighbor lead. these parameters are important in determining ground bounce noise and inductive crosstalk noise. three capacitances in pf are listed: c m , the mutual capaci- tance of the lead to the nearest neighbor lead; and c 1 and c 2 , the total capacitance of the lead to all other leads (all other leads are assumed to be grounded). these parameters are important in determining capaci- tive crosstalk and the capacitive loading effect of the lead. the parasitic values in table 18 are for the circuit model of bond wire and package lead parasitics. if the mutual capacitance value is not used in the designer? model, then the value listed as mutual capacitance should be added to each of the c1 and c2 capacitors. the pgas contain power and ground planes that will make the inductance value for power and ground leads the minimum value listed. the pgas also have a signif- icant range of parasitic values. this is due to the large variation in internal trace lengths and is also due to two signal metal layers that are separated from the ground plane by different distances. the upper signal layer is more inductive but less capacitive than the closer, lower signal layer.
data sheet att3000 series field-programmable gate arrays february 1997 52 lucent technologies inc. package parasitics (continued) * leads designated as ground (power) can be connected to the ground plane, reducing the trace inductance to the minimum value listed. figure 32. package parasitics table 18. package parasitics package type l w m w r w c 1 c 2 c m l l m l 44-pin plcc 3 1 140 0.5 0.5 0.3 5? 2?.5 68-pin plcc 3 1 140 0.5 0.5 0.4 6? 3? 84-pin plcc 3 1 140 1 1 0.5 7?1 3? 100-pin qfp 3 1 160 1 1 0.5 7? 4? 100-pin tqfp 3 1 150 0.5 0.5 0.4 4? 2? 132-pin ppga 3 1 150 1 1 0.25 4?0 0.5? 144-pin tqfp 3 1 140 1 1 0.6 4? 2?.5 160-pin qfp 4 1.5 180 1.5 1.5 1 10?3 6? 175-pin ppga 3 1 150 1 1 0.3 5?1 1?.5 208-pin sqfp 4 2 200 1 1 1 7?0 4? 5-3862(c) pad n l w r w circuit board pad c m c 1 l w r w l l l mw c 2 c 1 l ml c 2 l l pad n + 1
data sheet february 1997 att3000 series field-programmable gate arrays lucent technologies inc. 53 absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are abso- lute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. parameter symbol min max unit supply voltage relative to gnd v cc ?.5 7.0 v input voltage relative to gnd v in ?.5 0.5 v voltage applied to 3-state output v ts ?.5 0.5 v storage temperature (ambient) t stg ?5 150 ? maximum soldering temperature (10 seconds at 1/16 in.) t sol 260 ? junction temperature t j 125 ?
data sheet att3000 series field-programmable gate arrays february 1997 54 lucent technologies inc. electrical characteristics * sample tested. note: with no output current loads, no active input or long-line pull-up resistors, all package pins at v cc or gnd, and the fpga con?ured with a bit stream generation program tie option. table 19. dc electrical characteristics over operating conditions commercial: v cc = 5.0 v ?5%; 0 ? t a 70 ?; industrial: v cc = 5.0 ?10%, ?0 ? t a +85 ?. parameter/conditions symbol -50, -70, -100, and -125 -3, -4, and -5 unit min max min max high-level input voltage cmos level ttl level v ihc v iht 70% 2.0 100% v cc 70% 2.0 100% v cc v v low-level input voltage cmos level ttl level v ilc v ilt 0 0 20% 0.8 0 0 20% 0.8 v v output voltage high (i oh = ? ma) (i oh = ? ma) low (i ol = 4 ma) (i ol = 8 ma) v oh v oh v ol v ol 3.86 0.40 3.86 0.40 v v v v input signal transition time t in 250 250 ns powerdown supply current att3020 att3030 att3042 att3064 att3090 i ccpd 50 80 120 170 250 50 80 120 170 250 ? ? ? ? ? quiescent fpga supply current (in addition to iccpd) cmos inputs att3020 att3030 att3042 att3064 att3090 ttl inputs i cco 500 500 500 500 500 10 10 500 500 500 500 500 20 ma ? ? ? ? ? ma leakage current i il ?0 10 ?0 10 ? input capacitance* all packages except 175-pga: all pins except xtl1/xtl2 xtl1 and xtl2 175-pga package: all pins except xtl1/xtl2 xtl1 and xtl2 c in 10 15 15 20 10 15 15 20 pf pf pf pf pad pull-up* (when selected) (at v in = 0 v) i rin 0.02 0.17 0.02 0.17 ma horizontal long-line pull-up (when selected) at logic low i rll 0.2 2.5 0.2 2.8 ma
data sheet february 1997 att3000 series field-programmable gate arrays lucent technologies inc. 55 electrical characteristics (continued) * these parameters are for clock pulses within an fpga device. for externally applied clock, increase values by 20%. note: the clb k to q output delay (tcko?8) of any clb, plus the shortest possible interconnect delay, is always longer than the data in hold time requirement (tckdi?5) of any clb on the same die. table 20. clb switching characteristics (-50, -70, -100, and -125) commercial: v cc = 5.0 v ?5%; 0 ? t a 70 ?; industrial: v cc = 5.0 ?10%, ?0 ? t a +85 ?. description symbol -50 -70 -100 -125 unit min max min max min max min max combinatorial delay 1 t ilo 14.0 9.0 7.0 5.5 ns sequential delay clock k to outputs x or y clock k to outputs x or y when q returned through function generators f or g to drives x or y 8 t cko t qlo 12.0 23.0 6.0 13.0 5.0 10.0 4.5 8.0 ns ns setup time logic variables data in enable clock reset direct active 2 4 6 t ick t dick t ecck t rdck 12.0 8.0 10.0 1.0 8.0 5.0 7.0 1.0 7.0 4.0 5.0 1.0 5.5 3.0 4.5 1.0 ns ns ns ns hold time logic variables data in enable clock 3 5 7 t cki t ckdi t ckec 1.0 6.0 0 0 4.0 0 0 2.0 0 0 1.5 0 ns ns ns clock high time* low time* flip-flop toggle rate* 11 12 t ch t cl f clk 9.0 9.0 50 5.0 5.0 70 4.0 4.0 100 3.0 3.0 125 ns ns mhz reset direct (rd) rd width delay from rd to outputs x, y 13 9 t rpw t rio 12.0 12.0 8.0 8.0 7.0 7.0 6.0 6.0 ns ns master reset (mr) mr width delay from mr to outputs x, y t mrw t mrq 30 27 25 23 21 19 20 17 ns ns
data sheet att3000 series field-programmable gate arrays february 1997 56 lucent technologies inc. electrical characteristics (continued) * these parameters are for clock pulses within an fpga device. for externally applied clock, increase values by 20%. note: the clb k to q output delay (tcko?8) of any clb, plus the shortest possible interconnect delay, is always longer than the data in hold time requirement (tckdi?5) of any clb on the same die. table 21. clb switching characteristics (-3, -4, and -5) commercial: v cc = 5.0 v ?5%; 0 ? t a 70 ?; industrial: v cc = 5.0 ?10%, ?0 ? t a +85 ?. description symbol -5 -4 -3 unit min max min max min max combinatorial delay 1 t ilo 4.1 3.3 2.7 ns sequential delay clock k to outputs x or y clock k to outputs x or y when q returned through function generators f or g to drives x or y 8 t cko t qlo 3.1 6.3 2.5 5.2 2.1 4.3 ns ns setup time logic variables data in enable clock reset direct active 2 4 6 t ick t dick t ecck t rdck 3.1 2.0 3.8 1.0 2.5 1.6 3.2 1.0 2.1 1.4 2.7 1.0 ns ns ns ns hold time logic variables data in enable clock 3 5 7 t cki t ckdi t ckec 0 1.2 1.0 0 1.0 0.8 0 0.9 0.7 ns ns ns clock high time* low time* flip-flop toggle rate* 11 12 t ch t cl f clk 2.4 2.4 190 2.0 2.0 230 1.6 1.6 270 ns ns mhz reset direct (rd) rd width delay from rd to outputs x, y 13 9 t rpw t rio 3.8 4.4 3.2 3.7 2.7 3.1 ns ns master reset (mr) mr width delay from mr to outputs x, y t mrw t mrq 18.0 17.0 15.0 14.0 13.0 12.0 ns ns
data sheet february 1997 att3000 series field-programmable gate arrays lucent technologies inc. 57 electrical characteristics (continued) figure 33. clb switching characteristics clb output (x,y) clb input clb clock clb input clb input clb output t ilo clb input (combinatorial) (a, b, c, d, e) (direct in) (enable clock) (flip-flop) (reset direct) clb output (flip-flop) t ick t cki t cl t dick t ch t ckdi t ecck t ckec t cko t rpw t rio 1 12 3 2 11 5 4 7 6 8 13 9 5-3124(f)
data sheet att3000 series field-programmable gate arrays february 1997 58 lucent technologies inc. electrical characteristics (continued) * these parameters are for clock pulses within an fpga device. for externally applied clock, increase values by 20%. notes: timing is measured at pin threshold with 50 pf external capacitive loads (including test ?ture). typical fast mode output rise/fall times are 2 ns and will increase approximately 2%/pf of additional load. typical slew-rate limited output rise/fall times are approximately 4 times longer. a maximum total external capacitive load for simultaneous fast mode switching in the same direction is 200 pf per power/ground pin pair. for slew-rate limited outputs, this total is 4 times larger. exceeding this maximum capacitive load can result in ground bounce of >1.5 v amplitude and <5 ns duration, which may cause problems when the fpga drives clocks and other asynchronous signals. voltage levels of unused (bonded and unbonded) pads must be valid logic levels. each can be con?ured with the internal pull-up resistor or alternatively con?ured as a driven output or driven from an external source. input pad setup time is speci?d with respect to the internal clock (ik). to calculate system setup time, subtract clock delay (pad to ik) from the input pad setup time value. input pad hold time with respect to the inter- nal clock (ik) is negative. this means that pad levels changed immediately before the internal clock edge (ik) will not be recognized. table 22. iob switching characteristics (-50, -70, -100, and -125) commercial: v cc = 5.0 v ?5%; 0 ? t a 70 ?; industrial: v cc = 5.0 ?10%, ?0 ? t a +85 ?. description symbol -50 -70 -100 -125 unit min max min max min max min max input delays pad to direct in pad to registered in clock to registered in 3 4 t pid t ptg t ikri 9.0 34.0 11.0 6.0 21.0 5.5 4.0 17.0 4.0 3.0 16.0 3.0 ns ns ns setup time (input): clock setup time 1 t pick 30.0 20.0 17.0 16.0 ns output delays clock to pad fast slew-rate limited output to pad fast slew-rate limited 3-state to pad hi-z fast slew-rate limited 3-state to pad valid fast slew-rate limited 7 7 10 10 9 9 8 8 t okpo t okpo t opf t ops t tshz t tshz t tson t tson 18.0 43.0 15.0 40.0 10.0 37.0 20.0 45.0 13.0 33.0 9.0 29.0 8.0 28.0 14.0 34.0 10.0 27.0 6.0 23.0 8.0 25.0 12.0 29.0 9.0 24.0 5.0 20.0 7.0 24.0 11.0 27.0 ns ns ns ns ns ns ns ns setup and hold times (out- put) clock setup time clock hold time 5 6 t ock t oko 15.0 0 10.0 0 9.0 0 8.0 0 ns ns clock high time* low time* max. flip-flop toggle* 11 12 t ch t cl f clk 9.0 9.0 50 5.0 5.0 70 4.0 4.0 100 3.0 3.0 125 ns ns mhz master reset delays reset to: registered in output pad (fast) output pad (slew- rate limited) 13 15 15 t rri t rpo t rpo 35 50 68 25 35 53 24 33 45 23 29 42 ns ns ns
data sheet february 1997 att3000 series field-programmable gate arrays lucent technologies inc. 59 electrical characteristics (continued) * these parameters are for clock pulses within an fpga device. for externally applied clock, increase values by 20%. notes: timing is measured at pin threshold with 50 pf external capacitive loads (including test ?ture). typical fast mode output rise/fall times are 2 ns and will increase approximately 2%/pf of additional load. typical slew-rate limited output rise/fall times are approximately 4 times longer. a maximum total external capacitive load for simultaneous fast mode switching in the same direction is 200 pf per power/ground pin pair. for slew-rate limited outputs, this total is 4 times larger. exceeding this maximum capacitive load can result in ground bounce of >1.5 v amplitude and <5 ns duration, which may cause problems when the fpga drives clocks and other asynchronous signals. voltage levels of unused (bonded and unbonded) pads must be valid logic levels. each can be con?ured with the internal pull-up resistor or alternatively con?ured as a driven output or driven from an external source. input pad setup time is speci?d with respect to the internal clock (ik). to calculate system setup time, subtract clock delay (pad to ik) from the input pad setup time value. input pad hold time with respect to the internal clock (ik) is negative. this means that pad levels changed immediately before the internal clock edge (ik) will not be recognized. table 23. iob switching characteristics (-3, -4, and -5) commercial: v cc = 5.0 v ?5%; 0 ? t a 70 ?; industrial: v cc = 5.0 ?10%, ?0 ? t a +85 ?. description symbol -5 -4 -3 unit min max min max min max input delays pad to direct in pad to registered in clock to registered in 3 4 t pid t ptg t ikri 2.8 16.0 2.8 2.5 15.0 2.5 2.2 13.0 2.2 ns ns ns setup time (input): clock setup time 1 t pick 15.0 14.0 12.0 ns output delays clock to pad fast slew-rate limited output to pad fast slew-rate limited 3-state to pad hi-z fast slew-rate limited 3-state to pad valid fast slew-rate limited 7 7 10 10 9 9 8 8 t okpo t okpo t opf t ops t tshz t tshz t tson t tson 5.5 14.0 4.1 13.0 6.9 21.0 12.0 20.0 5.0 12.0 3.7 11.0 6.2 19.0 10.0 17.0 4.4 10.0 3.3 9.0 5.5 17.0 9.0 15.0 ns ns ns ns ns ns ns ns setup and hold times (output) clock setup time clock hold time 5 6 t ock t oko 6.2 0 5.6 0 5.0 0 ns ns clock high time* low time* max. flip-flop toggle* 11 12 t ch t cl f clk 2.4 2.4 190 2.0 2.0 230 1.6 1.6 270 ns ns mhz master reset delays reset to: registered in output pad (fast) output pad (slew- rate limited) 13 15 15 t rri t rpo t rpo 18 24 32 15 20 27 13 17 23 ns ns ns
data sheet att3000 series field-programmable gate arrays february 1997 60 lucent technologies inc. electrical characteristics (continued) figure 34. iob switching characteristics i/o block (i) i/o pad input i/o clock i/o block (ri) reset i/o block (o) i/o pad output i/o pad output (ik/ok) (direct) (registered) i/o pad ts i/o pad output t pid t pick t ikpi t ch t cl t ikri t rri t oko t ock t op t okpo t tshz t tson 3 1 4 12 11 13 15 t rpo 6 5 7 10 8 9 2 5-3126(f)
data sheet february 1997 att3000 series field-programmable gate arrays lucent technologies inc. 61 electrical characteristics (continued) * timing is based on the att3042; for other devices, see timing calculator in orca foundry. table 24. buffer (internal) switching characteristics commercial: v cc = 5.0 v ?5%; 0 ? t a 70 ?; industrial: v cc = 5.0 ?10%, ?0 ? t a +85 ?. description symbol -50 -70 -100 -125 -5 -4 -3 unit max max max max max max max global and alternate clock distribution*: either normal iob input pad to clock buffer input or fast (cmos only) input pad to clock buffer input t pid t pidc 10.0 8.0 8.0 6.5 7.5 6.0 7.0 5.7 6.8 5.4 6.5 5.1 5.6 4.3 ns ns tbuf driving a horizontal long line (ll)*: i to ll while t is low (buffer active) t to ll active and valid with single pull-up resistor t to ll active and valid with pair of pull-up resistors t - to ll high with single pull-up resistor t - to ll high with pair of pull-up resistors t io t on t on t pus t puf 8.0 12.0 14.0 42.0 22.0 5.0 11.0 12.0 24.0 17.0 4.7 10.0 11.0 22.0 15.0 4.5 9.0 10.0 17.0 12.0 4.1 5.6 7.1 15.6 12.0 3.7 5.0 6.5 13.5 10.5 3.1 4.2 5.7 11.4 8.8 ns ns ns ns ns bidirectional buffer delay t bidi 6.0 2.0 1.8 1.7 1.4 1.2 1.0 ns
data sheet att3000 series field-programmable gate arrays february 1997 62 lucent technologies inc. electrical characteristics (continued) * at powerup, v cc must rise from 2 v to v cc minimum in less than 25 ms. if this is not possible, con?uration can be delayed by holding reset low until v cc has reached 4 v. a very long v cc rise time of >100 ms or a nonmonotonically rising v cc may require a >1 ? high level on reset , followed by a >6 ? low level on reset and done/ prog after v cc has reached 4 v. figure 35. general fpga switching characteristics testing of the switching characteristics is modeled after testing speci?d by mil-m-38510/605. devices are 100% functionally tested. actual worst-case timing is provided by the timing calculator or simulation. * reset timing relative to valid mode lines (m0, m1, m2) is relevant when reset is used to delay configuration. ? pwrdwn transitions must occur while v cc > 4 v. table 25. general fpga switching characteristics signal description symbol min max unit reset * m0, m1, and m2 setup time m0, m1, and m2 hold time reset width (low) required for abort t mr (2) t rm (3) t mrw (4) 1 4.5 6 ? ? ? done/ pr og width low required for recon?uration init response after done/ pr og is pulled low t pgw (5) t pgi (6) 6 7 ? ? v cc ? powerdown v cc ( commercial/industrial) v ccpd 2.3 v reset m0/m1/m2 done/prog init (output) t mrw pwrdwn valid v cc (valid) t mr t rm t pgw t pgi user state configure clear state see * v ccpd 2 5 3 6 4 5-3124(f)
data sheet february 1997 att3000 series field-programmable gate arrays lucent technologies inc. 63 electrical characteristics (continued) figure 36. master serial mode switching characteristics notes: at powerup, v cc must rise from 2.0 v to v cc minimum in less than 25 ms. if this is not possible, con?uration can be delayed by holding reset low until v cc has reached 4.0 v. a very long v cc rise time of >100 ms, or a nonmonotonically rising v cc may require a >1 ? high level on reset , followed by >6 ? low level on reset and d/ p after v cc has reached 4.0 v. con?uration can be controlled by holding reset low with or until after the init of all daisy-chain slave mode devices is high. master serial mode timing is based on slave mode testing. table 26. master serial mode switching characteristics signal description symbol min max unit cclk data-in setup data-in hold 1 2 t dsck t ckds 60 0 ns ns t dsck t ckds cclk (output) serial din serial dout (output) 1 2 5-3127(f).a
data sheet att3000 series field-programmable gate arrays february 1997 64 lucent technologies inc. electrical characteristics (continued) note: the eprom requirements in this timing diagram are extremely relaxed; eprom access time can be longer than 4000 ns. eprom data output has no hold time requirements. figure 37. master parallel mode switching characteristics notes: at powerup, v cc must rise from 2.0 v to v cc minimum in less than 25 ms. if this is not possible, con?uration can be delayed by holding reset low until v cc has reached 4.0 v. a very long v cc rise time of >100 ms, or a nonmonotonically rising v cc may require a >1 ? high level on reset , followed by >6 ? low level on reset and d/ p after v cc has reached 4.0 v. con?uration can be controlled by holding reset low with or until after the init of all daisy-chain slave mode devices is high. table 27. master parallel mode switching characteristics signal description symbol min max unit rclk to address valid to data setup to data hold rclk high rclk low 1 2 3 t rac t drc t rcd t rch t rcl 0 60 0 600 4.0 200 ns ns ns ns ? a[15:0] d[7:0] rclk cclk (output) address for byte n + 1 address for byte n (output) dout (output) byte n d6 d7 t rac t drc t rcd cclk 7 cclks byte n ?1 2 3 1 5-3128(f)
data sheet february 1997 att3000 series field-programmable gate arrays lucent technologies inc. 65 electrical characteristics (continued) note: the requirements in this timing diagram are extremely relaxed; data need not be held beyond the rising edge of ws . busy will go active within 60 ns after the end of ws . busy will stay active for several microseconds. ws may be asserted immediately after the end of busy . figure 38. peripheral mode switching characteristics notes: at powerup, v cc must rise from 2.0 v to v cc minimum in less than 25 ms. if this is not possible, con?uration can be delayed by holding reset low until v cc has reached 4.0 v. a very long v cc rise time of >100 ms, or a nonmonotonically rising v cc may require a >1 ? high level on reset , followed by >6 ? low level on reset and d/ p after v cc has reached 4.0 v. con?uration must be delayed until the init of all fpgas is high. time from end of ws to cclk cycle for the new byte of data depends on completion of previous byte processing and the phase of the internal timing generator for cclk. cclk and dout timing is tested in slave mode. t busy indicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data. the shortest t busy occurs when a byte is loaded into an empty parallel-to-serial converter. the longest t busy occurs when a new word is loaded into the input register before the second-level buffer has started shifting out data. table 28. peripheral mode switching characteristics signal description symbol min max unit write signal effective write time required (assertion of cs0 , cs1 , cs2, ws ) 1 t ca 100 ns d[7:0] din setup time required din hold time required 2 3 t dc t cd 60 0 ns ns rdy/ b usy rdy/ b usy delay after end of ws earliest next ws after end of b usy b usy low time generated 4 5 6 t wtrb t rbwt t busy 0 2.5 60 9 ns ns cclk periods 5-3129(f) cs1/cs0 cs2 ws d[7:0] cclk rdy/busy dout t ca t dc t cd valid t rbwt t wtrb t busy group of 8 cclks 1 4 3 6 5 2
data sheet att3000 series field-programmable gate arrays february 1997 66 lucent technologies inc. electrical characteristics (continued) figure 39. slave mode switching characteristics notes: the maximum limit of cclk low time is caused by dynamic circuitry inside the fpga device. con?uration must be delayed until the init of all fpgas is high. at powerup, v cc must rise from 2.0 v to v cc minimum in less than 25 ms. if this is not possible, con?uration can be delayed by holding reset low until v cc has reached 4.0 v. a very long v cc rise time of >100 ms, or a nonmonotonically rising v cc , may require a >1 ? high level on reset , followed by >6 ? low level on reset and d/ p after v cc has reached 4.0 v. table 29. slave mode switching characteristics commercial: v cc = 5.0 v ?5%; 0 ? t a 70 ?; industrial: v cc = 5.0 ?10%, ?0 ? t a +85 ?. signal description symbol min max unit cclk to dout din setup din hold high time low time frequency 3 1 2 4 5 t cco t dcc t ccd t cch t ccl f cc 60 0 0.05 0.05 100 5.0 10.0 ns ns ns ? ? mhz t dcc din cclk dout (output) t ccd bit n t cch bit n ?1 bit n + 1 t ccl bit n t cco 1 2 4 5 3 5-3130(f)
data sheet february 1997 att3000 series field-programmable gate arrays lucent technologies inc. 67 electrical characteristics (continued) figure 40. program readback switching characteristics notes: during readback, cclk frequency may not exceed 1 mhz. rtrig (m0 positive transition) must not be done until after one clock following active i/o pins. readback should not be initiated until after con?uration is complete. table 30. program readback switching characteristics commercial: v cc = 5.0 v ?5%; 0 ? t a 70 ?; industrial: v cc = 5.0 ?10%, ?0 ? t a +85 ?. signal description symbol min max unit rtrig rtrig high 1 t rth 250 ns cclk rtrig setup rd a t a delay high time low time 2 3 5 4 t rtcc t ccrd t cch t ccl 200 0.5 0.5 100 5.0 ns ns ? ? t rth done/prog rtrig (m0) cclk (1) t ccl (output) rdata (output) valid t rtcc t ccl t ccrd 1 4 2 4 3 5-3131(f)
data sheet att3000 series field-programmable gate arrays february 1997 68 lucent technologies inc. outline diagrams terms and de?itions basic size (bsc): the basic size of a dimension is the size from which the limits for that dimension are derived by the application of the allowance and the tolerance. design size: the design size of a dimension is the actual size of the design, including an allowance for ? and tolerance. typical (typ): when speci?d after a dimension, indicates the repeated design size if a tolerance is speci- ?d or repeated basic size if a tolerance is not speci?d. reference (ref): the reference dimension is an untoleranced dimension used for informational purposes only. it is a repeated dimension or one that can be derived from other values in the drawing. minimum (min) or maximum (max): indicates the minimum or maximum allowable size of a dimension. 44-pin plcc dimensions are in millimeters. 5-2506r7(c) 4.57 max 1.27 typ 0.53 max 0.10 seating plane 0.51 min typ 1 6 40 7 17 29 39 18 28 pin #1 identifier zone 16.66 max 17.65 max 16.66 max 17.65 max
data sheet february 1997 att3000 series field-programmable gate arrays lucent technologies inc. 69 outline diagrams (continued) 68-pin plcc dimensions are in millimeters. 5-2139r13(c) 1 9 10 26 27 43 44 60 61 pin #1 identifier zone 25.27 max 24.33 max 25.27 max 24.33 max 1.27 typ 0.53 max 5.08 max 0.51 min, typ seating plane 0.10
data sheet att3000 series field-programmable gate arrays february 1997 70 lucent technologies inc. outline diagrams (continued) 84-pin plcc dimensions are in millimeters. 5-2347r13(c) 5.08 max 1.27 typ 0.53 max 0.10 seating plane 0.51 min typ pin #1 identifier zone 11 75 53 33 12 32 54 74 29.16 max 30.35 max 30.35 max 29.16 max 1
data sheet february 1997 att3000 series field-programmable gate arrays lucent technologies inc. 71 outline diagrams (continued) 100-pin qfp dimensions are in millimeters. 5-2131r9(c) detail a detail b 3.30 max 0.65 typ seating plane 0.10 2.80 ?0.25 0.25 max 1 30 51 80 81 100 pin #1 identifier zone 17.20 ?0.20 14.00 ?0.20 20.00 ?0.20 23.20 ?0.20 50 31 0.22/0.38 0.12 m 0.13/0.23 detail b 0.25 0.73/1.03 1.60 ref gage plane seating plane detail a
data sheet att3000 series field-programmable gate arrays february 1997 72 lucent technologies inc. outline diagrams (continued) 100-pin tqfp dimensions are in millimeters. 5-2146r14(c) 0.50 typ 1.60 max seating plane 0.08 1.40 ?0.05 0.05/0.15 detail a detail b 14.00 ?0.20 16.00 ?0.20 76 100 1 25 26 50 51 75 14.00 ?0.20 16.00 ?0.20 pin #1 identifier zone detail b 0.19/0.27 0.08 m 0.106/0.200 detail a 0.45/0.75 gage plane seating plane 1.00 ref 0.25
data sheet february 1997 att3000 series field-programmable gate arrays lucent technologies inc. 73 outline diagrams (continued) 132-pin ppga dimensions are in millimeters. 5-2115(c) typical thermal via package id 37.08 ?0.38 37.08 ?0.38 pin a1 index mark a b c d e f g h j k l m n p 1 2 3 4 5 6 8 9 10 11 12 13 14 7 13 spaces @ 2.54 = 33.02 13 spaces @ 2.54 = 33.02 pin a1 corner 2.16 ?0.23 1.19 ?0.20 0.46 ?0.05 1.78 ?0.20 typ 4 places 5.21 ?0.20
data sheet att3000 series field-programmable gate arrays february 1997 74 lucent technologies inc. outline diagrams (continued) 144-pin tqfp dimensions are in millimeters. 5-3815r5(c) 1.60 max seating plane 0.08 0.50 typ 1.40 ?0.05 0.05/0.15 detail a detail b pin #1 identifier zone 20.00 ?0.20 22.00 ?0.20 109 144 1 36 37 72 73 108 20.00 ?0.20 22.00 ?0.20 detail b 0.19/0.27 0.08 m 0.106/0.200 detail a 0.45/0.75 gage plane seating plane 1.00 ref 0.25
data sheet february 1997 att3000 series field-programmable gate arrays lucent technologies inc. 75 outline diagrams (continued) 160-pin qfp dimensions are in millimeters. 5-2132r12(c) 40 41 80 81 120 121 1 pin #1 identifier zone 31.20 ?0.20 28.00 ?0.20 28.00 ?0.20 31.20 ?0.20 0.10 seating plane 3.42 ?0.25 0.25 min 0.65 typ 4.07 max detail a detail b 0.25 1.60 ref gage plane seating plane 0.73/1.03 detail a 0.22/0.38 0.12 m 0.13/0.23 detail b
data sheet att3000 series field-programmable gate arrays february 1997 76 lucent technologies inc. outline diagrams (continued) 175-pin ppga dimensions are in inches. 5-2116(c) 5.21 ?0.20 2.16 ?0.23 1.78 ?0.20 typ 4 places 0.46 ?0.05 1.19 ?0.20 pin a1 indicator index mark 42.16 ?0.40 typical thermal via package id 42.16 ?0.40 15 spaces @ 2.54 = 38.10 3 4 5 6 7 8 9 10 11 13 14 15 2 12 16 1 s r p n m l k j h g f e c b a d pin a1 corner 15 spaces @ 2.54 = 38.10
data sheet february 1997 att3000 series field-programmable gate arrays lucent technologies inc. 77 outline diagrams (continued) 208-pin sqfp dimensions are in millimeters. 156 105 30.60 ?0.20 157 208 1 52 53 104 28.00 ?0.20 28.00 ?0.20 30.60 ?0.20 pin #1 identifier zone 4.10 max 0.10 3.40 ?0.20 seating plane 0.25 min 0.50 typ detail b detail a 0.50/0.75 gage plane seating plane 1.30 ref 0.25 detail a detail b 0.17/0.27 0.10 m 0.090/0.200 5-2196(c)r12
data sheet att3000 series field-programmable gate arrays february 1997 78 lucent technologies inc. ordering information the att3000 series includes standard and high- performance fpgas. the part nomenclature uses two different suf?es for speed designation. the lower- speed att3000 series devices use a ?p-?p toggle rate (-50, -70, -100, -125), which corresponds to xc3000 series nomenclature. the att3000 series high-performance fpgas use a suf? which is an approximation of the look-up table delay (-5, -4, and -3), which corresponds to xc3100 nomenclature. for packaging options, burn-in diagrams, and/or pack- age assembly information, call 1-800-easy-fpg(a) or 1-800-327-9374. example: att3020, 100 mhz, 68-lead plcc, industrial temperature table 31. fpga temperature options symbol description temperature (blank) commercial 0 ? to 70 ? i industrial ?0 ? to +85 ? table 32. fpga package options symbol description h plastic pin grid array j quad flat pack m plastic leaded chip carrier s shrink quad flat pack t thin quad flat pack a tt3020 -100 m 68 device type toggle rate package type number of pins temperature range i
data sheet february 1997 att3000 series field-programmable gate arrays lucent technologies inc. 79 ordering information (continued) key: c = commercial, i = industrial. table 33. att3000 series package matrix device speed 44-pin plcc 68-pin plcc 84-pin plcc 100-pin 132-pin ppga 144-pin tqfp 160-pin qfp 175-pin ppga 208-pin sqfp qfp tqfp m44 m68 m84 j100 t100 h132 t144 j160 h175 s208 att3020 -70 ci ci ci -100 ci ci ci -125 ci ci ci -5 ci ci ci -4 c c c -3 c c c att3030 -70 ci ci ci ci ci -100 ci ci ci ci ci -125 ci ci ci ci ci -5 ci ci ci ci ci -4 c c c c c -3 c c c c c att3042 -70 ci ci ci ci ci -100 ci ci ci ci ci -125 ci ci ci ci ci -5 ci ci ci ci ci -4 c c c c c -3 c c c c c att3064 -70 ci ci ci ci ci -100 ci ci ci ci ci -125 ci ci ci ci ci -5 ci ci ci ci ci -4 c c c c c -3 c c c c c att3090 -70 ci ci ci ci -100 ci ci ci ci -125 ci ci ci ci -5 ci ci ci ci -4 c c c c -3 c c c c
data sheet att3000 series field-programmable gate arrays february 1997 for fpga technical applications support, please call 1-800-327-9374. outside the u.s.a., please call 1-610-712-4331. for additional information, contact your microelectronics group account manager or the following: internet: http://www.lucent.com/micro/fpga u.s.a.: microelectronics group, lucent technologies inc., 555 union boulevard, room 30l-15p-ba, allentown, pa 18103 1-800-372-2447 , fax 1-610-712-4106 (in canada: 1-800-553-2448 , fax 1-610-712-4106), e-mail docmaster@micro.lucent.com asia pacific: microelectronics group, lucent technologies singapore pte. ltd., 77 science park drive, #03-18 cintech iii, singapore 118256 tel. (65) 778 8833 , fax (65) 777 7495 japan: microelectronics group, lucent technologies semiconductor marketing ltd., 2-7-18, higashi-gotanda, shinagawa-ku, tokyo 141, japan tel. (81) 3 5421 1770 , fax (81) 3 5421 1785 for data requests in europe: microelectronics group dataline: tel. (44) 1734 324 299 , fax (44) 1734 328 148 for technical inquiries in europe: central europe: (49) 89 95086 0 (munich), northern europe: (44) 1344 865 900 (bracknell uk), france: (33) 1 41 45 77 00 (paris), southern europe: (39) 2 6601 1800 (milan) or (34) 1 807 1700 (madrid) lucent technologies inc. reserves the right to make changes to the product(s) or information contained herein without notice. no liability is assumed as a result of their use or application. no rights under any patent accompany the sale of any such product(s) or information. orca is a trademark of lucent technologies inc. foundry is a trademark of xilinx, inc. copyright ?1997 lucent technologies inc. all rights reserved printed in u.s.a. february 1997 ds97-048fpga (replaces ds94-177fpga)

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